ARM CoreLink GIC-500 Generic Interrupt Controller Technical Reference ManualRevision: r0p0
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3.12.2. Error Test Register

The GICD_ERRTESTR characteristics are:

Purpose

This register tests the integration of the ecc_fatal and axim_err signals.

Usage constraints

There are no usage constraints.

Configurations

Always present in the GIC-500.

Attributes

See the register summary in Table 3.14.

Figure 3.7 shows the bit assignments.

Figure 3.7. GICD_ERRTESTR bit assignments

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Table 3.16 shows the bit assignments.

Table 3.16. GICD_ERRTESTR bit assignments

Bits

Name

Description

[31:2]

-

Reserved.

[1][a]AXIM_errWrite 0b1 to this field to drive the axim_err pin to 0b1 for 1 cycle. You can use this bit for an integration test of the axim_err signal.

[0]

ECC_fatal

Write 0b1 to this field to drive the ecc_fatal pin to 0b1 for 1 cycle. You can use this bit for an integration test on the ecc_fatal signal.

[a] The existence of this field depends on the configuration of the GIC-500. If ITS and LPI support is not included, this field is Reserved and RAZ/WI.


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