3.13.2. Private Peripheral Interrupt Status Register

The GICR_PPISR characteristics are:


This register enables a core to access the status of the PPI inputs to the Distributor.


In systems with two security states, Non-secure accesses can only read the status of Non-secure Group 1 interrupts.

Usage constraints

There are no usage constraints.


Always present in the GIC-500.


See the register summary in Table 3.18.

Figure 3.10 shows the bit assignments.

Figure 3.10. GICR_PPISR bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Table 3.20 shows the bit assignments.

Table 3.20. GICR_PPISR bit assignments





PPI status

These bits return the actual status of the PPI input signals. That is, each bit is one when the corresponding PPI input is HIGH for the core whose register is being read. The position of each bit corresponds to the interrupt ID of the PPI. For example, bit[30] corresponds to PPI ID 30. The Interrupt Set-Pending Register, GICR_ISPENDR, and Interrupt Clear-Pending Register, GICR_ICPENDR, can also provide the PPI status but because you can write to these registers, they might not contain the true status of the PPI input signals.




Copyright © 2014 ARM. All rights reserved.ARM DDI 0516B