3.13.2. Private Peripheral Interrupt Status Register

The GICR_PPISR characteristics are:

Purpose

This register enables a core to access the status of the PPI inputs to the Distributor.

Note

In systems with two security states, Non-secure accesses can only read the status of Non-secure Group 1 interrupts.

Usage constraints

There are no usage constraints.

Configurations

Always present in the GIC-500.

Attributes

See the register summary in Table 3.18.

Figure 3.10 shows the bit assignments.

Figure 3.10. GICR_PPISR bit assignments

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Table 3.20 shows the bit assignments.

Table 3.20. GICR_PPISR bit assignments

Bits

Name

Description

[31:16]

PPI status

These bits return the actual status of the PPI input signals. That is, each bit is one when the corresponding PPI input is HIGH for the core whose register is being read. The position of each bit corresponds to the interrupt ID of the PPI. For example, bit[30] corresponds to PPI ID 30. The Interrupt Set-Pending Register, GICR_ISPENDR, and Interrupt Clear-Pending Register, GICR_ICPENDR, can also provide the PPI status but because you can write to these registers, they might not contain the true status of the PPI input signals.

[15:0]

-

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