A.3. Interrupt signals

Table A.3 shows the interrupt inputs for the GIC-500.

Table A.3. Interrupt signals

Signal[a]

TypeSource/destinationDescription
spi[variable]Input[b]Peripherals

SPI inputs. The least significant bit of this signal is bit 32, which corresponds to interrupt ID 32.

Note

This represents a change from ARM interrupt controllers such as GIC-400, where the LSB is bit 0, but still has ID 32.

ppi31_<x>[n:0]Input[c]Peripherals local to a corePPI ID31.
ppi30_<x>[n:0]PPI ID30. Typically the Non-secure physical timer.
ppi29_<x>[n:0]PPI ID29. Typically the Secure physical timer.
ppi28_<x>[n:0]

PPI ID28.

ppi27_<x>[n:0]

PPI ID27. Typically the virtual timer.

ppi26_<x>[n:0]PPI ID26. Typically the hypervisor timer.
ppi25_<x>[n:0]PPI ID25. Typically the virtual CPU interface maintenance interrupt.
ppi24_<x>[n:0]

PPI ID24. Typically the Cross Trigger Interface (CTI) interrupt.

ppi23_<x>[n:0]

PPI ID23. Typically the Performance Counter (PMU) overflow interrupt.

ppi22_<x>[n:0]PPI ID22. Typically the Debug Communications Channel (DCC) interrupt.
ppi21_<x>[n:0]PPI ID21.
ppi20_<x>[n:0]PPI ID20.
ppi19_<x>[n:0]PPI ID19.
ppi18_<x>[n:0]PPI ID18.
ppi17_<x>[n:0]PPI ID17.
ppi16_<x>[n:0]PPI ID16.

[a] n denotes the number of the last core in the cluster <x>.

[b] This input is either active HIGH level-sensitive, or triggered on a rising edge, depending on the software programming.

[c] All these inputs are either active LOW level-sensitive, or triggered on a rising edge, depending on the software programming.


Copyright © 2014 ARM. All rights reserved.ARM DDI 0516B
Non-ConfidentialID060914