A.6. AXI4 master interface signals

The GIC-500 provides a 64-bit wide AXI4 master interface. See the ARM® AMBA® AXI and ACE Protocol Specification.

AXI4 signals that are not implemented in the GIC-500 are not shown in Table A.6.

Table A.6. GIC-500 implementation of AXI4 master signals

AXI signal name

Type

Source/destination

Description

Write address channel signals

awaddr_m[47:0]

Output

AXI4 interconnect

Non-standard width with respect to the ARM® AMBA® AXI and ACE Protocol Specification

awid_m[5:0]

Output

Non-standard width with respect to the ARM® AMBA® AXI and ACE Protocol Specification

awvalid_m

Output

See the ARM® AMBA® AXI and ACE Protocol Specification

awready_m

Input

awlen_m[7:0]

Output

awsize_m[2:0]

Output

awburst_m[1:0]

Output

awprot_m[2:0]

Output

awcache_m[3:0]

Output

Write data channel signals

wstrb_m[7:0]OutputAXI4 interconnect

See the ARM® AMBA® AXI and ACE Protocol Specification

wdata_m[63:0]

Output

wlast_m

Output

wvalid_m

Outut

wready_m

Input

Write response channel signals

bid_m[5:0]

Input

AXI4 interconnect

Non-standard width with respect to the ARM® AMBA® AXI and ACE Protocol Specification

bvalid_m

Input

See the ARM® AMBA® AXI and ACE Protocol Specification

bready_mOutput

bresp_m[1:0]

Input

Read address channel signals

araddr_m[47:0]

Output

AXI4 interconnect

Non-standard width with respect to the ARM® AMBA® AXI and ACE Protocol Specification

arid_m[5:0]

Output

Non-standard width with respect to the ARM® AMBA® AXI and ACE Protocol Specification

arvalid_mOutputAXI4 interconnect

See the ARM® AMBA® AXI and ACE Protocol Specification

arlen_m[7:0]

Output

arsize_m[2:0]

Output

arburst_m[1:0]

Output

arprot_m[2:0]

Output

arcache_m[3:0]

Output

arready_m

Input

Read data channel signals

rid_m[5:0]

Input

AXI4 interconnect

Non-standard width with respect to the ARM® AMBA® AXI and ACE Protocol Specification

rresp_m[1:0]

Input

See the ARM® AMBA® AXI and ACE Protocol Specification

rdata_m[63:0]

Input
rvalid_mInput
rready_mOutput

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