A.2. Miscellaneous signals

Table A.2 shows the miscellaneous signals for the GIC-500.

Table A.2. Miscellaneous signals







Power controller

Controls whether the GIC-500 considers a core as its first choice for an SPI that targets multiple cores. ARM recommends that this signal is typically driven HIGH during normal operation and driven LOW during certain sleep states, such as retention, so the core is likely to stay in the sleep state for longer. If this signal is not used, it must be tied HIGH.

wake_request_<x>[n:0]OutputIndicates a directed interrupt is pending for a core that has set GICR_WAKER.ProcessorSleep. This signal is expected to cause the core to power up and subsequently re-enable processing interrupts.
ecc_fatalOutputSystem controllerIndicates an uncorrectable ECC error.
axim_errOutputIndicates a bus error received by the AXI4 master port, such as a SLVERR or DECERR.

[a] n denotes the number of the last core in the cluster <x>.

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