A.4. Test signals

Table A.4 shows the test signals for the GIC-500. These signals must all be LOW during normal operation.

Table A.4. Test signals

Signal

Type

Source/destination

Description

dftrstdisable

Input

DFT control logic

Reset disable. Disables the external reset input for test mode. When this signal is HIGH, it forces the internal active-LOW reset HIGH, bypassing the reset synchronizer.

dftse

Input

Scan enable. Disables clock gates for test mode.

dftcgen

InputClock gate enable. When this signal is HIGH, it forces all the clock gates on so that all internal clocks always run.

dftramhold

InputRAM hold. When this signal is HIGH, it forces all the RAM chip selects LOW, preventing accesses to the RAMs.

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