2.3.6. Power management

The GIC-500 supports the power down of cores and can itself be powered down. The GICR_WAKER registers provide bits to control functions associated with power management. The architecture recommends how these bits can be used. Some bits within the GICR_WAKER are global, rather than separate, for each Redistributor, as GIC-500 is a monolithic implementation. This means that the components are not distinct, but are instead tightly integrated. The GIC architecture allows such implementations to behave differently. See the ARM® Generic Interrupt Controller Architecture Specification version 3.0 for more information.

The GIC architecture defines the programming sequence to safely power down a core that is attached to a Distributor. This involves using the GICR_WAKER.ProcessorSleep bit. When all cores within a cluster have been powered down using the architectural sequence, you can power gate the AXI4-Stream interface for that cluster.

When powering down the GIC-500, with the exception of the LPI pending bits, software must preserve the state of the GIC-500. The state must be copied after the GIC-500 core power down sequence has completed to ensure that the pending information that is preserved is up to date.

You can preserve the LPI pending bits using the architectural Redistributor powerdown sequence, which ensures the memory pointed to by each GICR_PENDBASER contains the updated pending information for the LPIs. This involves using the GICR_WAKER.Sleep bit. When the GIC-500 is powered up again, you can program the GICR_PENDBASER registers to point to the same memory to reload the LPI pending status. If there is no requirement to reload the pending LPIs, ARM recommends that you zero the pending table and set the GICR_PENDBASER.PTZ bit to one to speed up the initialization of the GIC-500.

Note

  • GICR_WAKER.Sleep can only be set to one when:

    • All RD0s have GICR_WAKER.ProcessorSleep == 1.

    • All RD0s have GICR_WAKER.ChildrenAsleep == 1.

  • GICR_WAKER.ProcessorSleep can only be set to zero when:

    • GICR_WAKER.Sleep == 0.

    • GICR_WAKER.Quiescent == 0.

Before a core is powered down, you must set GICR_WAKER.ProcessorSleep to one and wait until GICR_WAKER.ChildrenAsleep is one to ensure there are no outstanding transactions on the AXI4-Stream interface of the core. In the typical powerdown sequence, to ensure that there are no interrupts during the powerdown of the core, you must:

  1. Mask interrupts on the core.

  2. Clear the CPU interface enables.

  3. Set the interrupt bypass disable on the CPU interface.

When a core has been powered down and the GICR_WAKER.ProcessorSleep bit is set to one, the GIC-500 attempts to wake the core if it receives an interrupt that targets only that core. It does this by asserting the wake_request signal corresponding to that core. This signal connects to the power controller. See Other core signals for more information about the wake_request signals.

You must not set GICR_WAKER.ProcessorSleep to one unless the core is entering a power state where the GIC-500 must use the power controller to wake the core rather than using the AXI4-Stream interface. For example, with Cortex-A53 and Cortex-A57, if the core is entering a sleep state based on the WFI or WFE instructions, such as retention, you must not set GICR_WAKER.ProcessorSleep to one. The core can enter these sleep states without software assistance. Given GICR_WAKER.ProcessorSleep is zero, the GIC-500 sends interrupts using the AXI4-Stream interface as normal. These interrupts can cause the core to leave the WFI or WFE instruction based on the standard rules in the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architectural profile. The system integrator can use the cpu_active signal to ensure that interrupts that can target multiple cores are much less likely to target cores in certain sleep states. In such a system, the software has more control over when cores leave sleep states.

Note

Interrupts that target only one core are unaffected by cpu_active and are always sent to that core. Moreover, if the GICR_WAKER.ProcessorSleep for that core is set, the wake_request signal is asserted for that core. See Other core signals for more information about the cpu_active signals.

See the ARM® Generic Interrupt Controller Architecture Specification version 3.0 for information about power management, and about wakeup signals and their relation to the core outputs.

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