2.2.1. AXI4 Slave Interface

One 32-bit AMBA AXI4 slave interface provides access to the programming interfaces of all parts of the GIC-500:

The slave interface also handles all message-based interrupts, which are interrupts generated by writes to the AXI4 slave interface. Message-based interrupts can generate SPIs or LPIs, depending on the register that you write to. See Interrupt types for information about the different types of interrupts.

The slave interface uses a single contiguous address region for all registers. See Chapter 3 Programmers Model for the address map.

Accesses to some registers requires sideband information. When using backwards compatibility mode, some registers are banked to provide a separate copy for each core. The system integrator must drive awuser_s[2:0] and aruser_s[2:0] with the binary number of the core performing the access for writes and reads, respectively.

Note

This information is only required for the first eight cores, because only this number of cores is supported in backwards compatibility mode. See Backwards compatibility for more information.

To generate an LPI a peripheral must write to the GITS_TRANSLATER. For the ITS to know which translations to apply to the generated interrupts, it must know which peripheral performed the write. The ID of the peripheral is known as its Device ID. ARM recommends that for a PCI Express (PCIe) peripheral, its GIC Device ID is its PCIe Requester ID without any modification. The AXI4 slave only requires the Device ID for writes to the GITS_TRANSLATER. For writes to that register, the GIC-500 supports two ways of receiving the Device ID:

Table 2.1 shows the AXI slave attributes and their values.

Table 2.1. AXI slave interface attributes

AttributeValue
Combined acceptance capability6
Read acceptance capability3
Read data reorder depth1
Write acceptance capability3

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