2.5. Constraints and limitations

ARM recommends that when ARE = 1 you avoid generating or disabling SPI interrupts that target multiple cores at times when no core is able to handle them. That is, disable or avoid generating such interrupts while all targeted CPU interfaces are either powered down or do not have the interrupt group enabled. This is because interrupts that are generated in these circumstances might cause higher power consumption inside GIC-500. The GIC architecture specifies that such interrupts do not cause a wake_request to become asserted so, in the absence of other stimulus, this state of higher power consumption persists.

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