2.2.2. AXI4 Master Interface

The GIC-500 uses the AXI4 master interface to access main memory. One 64-bit AMBA AXI4 master port is provided to allow the ITS and Redistributors to access main memory. The main memory holds the following:


The AXI master interface is not present if the ITS and LPI support are removed.

The hypervisor or OS software is responsible for allocating memory to the GIC-500. The GIC architecture also requires you to write software that zeros the allocated memory before use. Software must program registers in the ITS and Redistributors with the physical addresses of the allocated memory. Therefore the AXI4 master makes accesses using physical addresses and therefore does not require address translation such as a System Memory Management Unit (MMU).

When software has enabled the relevant functionality in the GIC-500, the software must not access the allocated memory again unless allowed by the GIC architecture. For example, memory programmed in the GITS_BASER must not be accessed when the ITS is enabled. However, the GIC architecture always permits software to write to the LPI configuration table pointed to by GICR_PROPBASER, and defines the INV and INVALL ITS commands that make the GIC use the new property values.

The GIC-500 does not support shareability, but does have programmable cacheability settings. Therefore the GIC-500 always treats memory as non-shareable. Software must discover this by attempting to write to the shareability and cacheability fields that are present in registers such as GICR_PROPBASER and by reading back the written values. The attributes in the MMU translation tables of the core must match those programmed in the GIC.

Consequently, software must issue the appropriate cache maintenance instructions when it wants to ensure that writes made by the core are visible to the GIC and when it wants to ensure that writes made by the GIC are visible to the core.

It is a system integration requirement that accesses that the GIC-500 makes to memory can complete without depending on any other accesses in the system making progress.

The AXI4 master interface only makes certain types of accesses. All transactions are 32 bytes or smaller, consisting of up to four transfers with up to eight bytes in each transfer. Only incrementing bursts are used. Accesses made by the AXI4 master involve the ITS and LPIs, which are always Non-secure. Therefore the AXI4 master always makes Non-secure accesses.

If the AXI4 master receives a bus error, such as SLVERR or DECERR, this is signaled through an external pin, axim_err. When this occurs, the GIC-500 might lose interrupts and cannot recover and you must reset the GIC-500. If it is not reset, the behavior becomes unpredictable.

Table 2.2 shows the AXI master attributes and their values.

Table 2.2. AXI master interface attributes

Combined issuing capability26
Read issuing capability11
Write issuing capability15

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