2.2.6. Other core signals

When a core is powered down, it must first disable the sending of packets over the AXI4-Stream interface using the GICR_WAKER.ProcessorSleep bit. When this has been done, the presence of an interrupt specifically targeted at that core causes the wake_request signal for that core to be asserted. ARM recommends that you connect this signal to the power controller to cause that core to boot. When the core has booted, software is always expected to re-enable communication over the interface through the use GICR_WAKER.ProcessorSleep, allowing the interrupt to be processed.

The GIC-500 uses the cpu_active signal to decide which cores are preferred for SPIs that target multiple cores. It does not affect the operation of any other type of interrupt. It also has no effect if GICR_WAKER.ProcessorSleep is set to one for that core, because those SPIs are never sent to cores with ProcessorSleep set to one. ARM recommends that this signal is deasserted when a core is in certain software-transparent sleep states entered during WFI or WFE instructions, such as retention, so that the core is less likely to handle SPIs that target multiple cores. This can increase the amount of time that cores spend in these sleep states. If you use the cpu_active signal this way, software must not rely on SPIs that target multiple cores causing cores to leave WFI or WFE. Instead, software must use another mechanism to ensure this, such as an SGI, or an SPI targeted at only the core in question.

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