1.1. About the GIC-500

The GIC-500 is a build-time configurable interrupt controller that supports up to 128 cores. The GIC-500 only supports cores that implement the ARMv8 architecture and the GIC CPU interface with the standard GIC Stream Protocol interface, such as Cortex®-A57 and Cortex-A53. It implements the ARM® Generic Interrupt Controller Architecture Specification version 3.0, to enable support for:

Figure 1.1 depicts the GIC-500 in an example system.

Figure 1.1. GIC-500 in an example system

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The GIC-500 receives interrupts from the AXI4 slave, or from physical inputs, depending on the type of interrupt. The GIC-500:

Connected ARM cores have System registers that provide the CPU interface to the GIC.

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