A.1. Clock and reset signals

Table A.1 shows the clock signals.

Note

The GIC-500 does not synchronize any inputs, so all input signals, including the SPI and PPI inputs, must be synchronous to clk.

Table A.1. Clock and reset signals

Signal name

Type

Source/destination

Description

clk

Input

Clock source

Common global clock signal for AXI and other interfaces. All clock gating is internal to the noram.

resetn

Input

Reset source

Common reset for all interfaces. Active LOW global asynchronous reset.

Reset must be asserted for at least (3 + number of synchronizer stages) clock cycles. For example, 3+2 = 5 cycles.


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