3.3. Distributor register summary

Address offsets are relative to the Distributor base address defined by the system memory map. Unless otherwise stated in the register description, all GIC-500 registers are 32 bits wide.

Table 3.3 lists the Distributor registers in base offset order and provides a reference to the register description that either this book or the ARM® Generic Interrupt Controller Architecture Specification version 3.0 describes.

Offsets that are not shown are Reserved and RAZ/WI.

Table 3.3. Distributor register summary

Offset

Name[a]

Type

Reset

Description[b]

0x0000

GICD_CTLR

RW

Configuration dependent[c]

Distributor Control Register

0x0004

GICD_TYPER

RO

Configuration dependent[d]

Interrupt Controller Type Register

0x0008

GICD_IIDR

RO

0x0000043B

Distributor Implementer Identification Register

0x000C-0x003C

-

-

-

Reserved

0x0040

GICD_SETSPI_NSR

WO

-

Non-secure SPI Set Register

0x0044

-

-

-

Reserved

0x0048

GICD_CLRSPI_NSR

WO

-

Non-secure SPI Clear Register

0x004C

-

-

-

Reserved

0x0050

GICD_SETSPI_SR[e]

WO

-

Secure SPI Set Register[f]

0x0054

-

-

-

Reserved

0x0058

GICD_CLRSPI_SR[e]

WO

-

Secure SPI Clear Register[f]
0x005C-0x007C

-

-

-

Reserved

0x0080-0x00F8

GICD_IGROUPRn

RW

0x00000000

Interrupt Group Registers[f]

0x0100

GICD_ISENABLERn

RW[g][h]

SGIs and PPIs: 0x0000FFFF[i][j][k][l]

Interrupt Set-Enable Registers

0x0104-0x0178SPIs: 0x00000000

0x0180

GICD_ICENABLERn

RW[g][m]

SGIs and PPIs: 0x0000FFFF[n][j][k][l]Interrupt Clear-Enable Registers
0x0184-0x01F8SPIs: 0x00000000

0x0200-0x0278

GICD_ISPENDRn[o]

RW

0x00000000

Interrupt Set-Pending Registers

0x0280-0x02F8

GICD_ICPENDRn[o]

RW

0x00000000

Interrupt Clear-Pending Registers

0x0300-0x0378

GICD_ISACTIVERn[o]

RW

0x00000000

Interrupt Set-Active Registers

0x0380-0x03F8

GICD_ICACTIVERn[o]

RW

0x00000000

Interrupt Clear-Active Registers

0x0400-0x07DC

GICD_IPRIORITYRn[p]

RW

0x00000000

Interrupt Priority Registers.

0x0800-0x081CGICD_ITARGETSRn[p]RO[q]-Interrupt Targets Registers[r]
0x0820-0x0BDCRW0x00000000
0x0C00GICD_ICFGRnROSGIs: 0xAAAAAAAA[l]Interrupt Configuration Registers
0x0C04RWPPIs: 0x00000000[l]
0x0C08-0x0CF4RW[s]SPIs: 0x00000000
0x0D00-0x0D78GICD_IGRPMODRn[e]RW0x00000000Interrupt Group Modifier Registers
0x0E00-0x0EF4GICD_NSACRn[e]RW0x00000000Non-secure Access Control Registers
0x0F00GICD_SGIR[t]WO-Software Generated Interrupt Register

0x0F10-0x0F1C

GICD_CPENDSGIRn[t]

RW

0x00000000

SGI Clear-Pending Registers

0x0F20-0x0F2C

GICD_SPENDSGIRn[e]

RW

0x00000000

SGI Set-Pending Registers

0x0F30-0x60FC

---Reserved

0x6100-0x7EF8

GICD_IROUTERn

RW

0x0000000000000000

Interrupt Routing Registers, 64-bit

0x7F00-0xBFFC

-

-

-

Reserved

0xC000GICD_ESTATUSRRO0x00000000

Extended Status Register

0xC004GICD_ERRTESTR WO-

Error Test Register

0xC008-0xC080---Reserved
0xC084-0xC0F8GICD_SPISRnRO-GIC-500 Shared Peripheral Interrupt Status Registers
0xC100- 0xFFCC---Reserved

0xFFD0

GICD_PIDR4

RO

0x00000044

Peripheral ID 4 Register

0xFFD4

GICD_PIDR5

RO

0x00000000

Peripheral ID 5 Register

0xFFD8

GICD_PIDR6

RO

0x00000000

Peripheral ID 6 Register

0xFFDC

GICD_PIDR7

RO

0x00000000

Peripheral ID 7 Register

0xFFE0

GICD_PIDR0

RO

0x00000092[u]

Peripheral ID 0 Register

0xFFE4

GICD_PIDR1

RO

0x000000B4

Peripheral ID 1 Register

0xFFE8

GICD_PIDR2

RO

0x0000003B

Peripheral ID2 Register

0xFFEC

GICD_PIDR3

RO

0x00000000

Peripheral ID 3 Register

0xFFF0

GICD_CIDR0

RO

0x0000000D

Component ID 0 Register

0xFFF4

GICD_CIDR1

RO

0x000000F0

Component ID 1 Register

0xFFF8

GICD_CIDR2

RO

0x00000005

Component ID 2 Register

0xFFFC

GICD_CIDR3

RO

0x000000B1

Component ID 3 Register

[a] n denotes that there are multiple registers.

[b] For the description of the registers that are not specific to the GIC-500, see the ARM® Generic Interrupt Controller Architecture Specification version 3.0.

[c] The reset value depends on the configuration of the GIC-500.

In systems that include Security Support, the values of the configuration dependent fields of GICD_CTLR are:

DS, bit[6] - 0.

ARE_NS, bit[5] - no GICv2 backwards compatibility support included.

ARE_S, bit[4] - no GICv2 backwards compatibility support included.

In systems that do not include Security Support, the values of the configuration dependent fields of GICD_CTLR are:

DS, bit[6] - 1.

ARE, bit[4] - no GICv2 backwards compatibility support included.

[d] The reset value depends on the configuration of the GIC-500. The values of the configuration dependent fields of the GICD_TYPER are:

A3V, bit[24] - 0.

IDbits, bits[23:19] - 0b01111.

DVIS, bit[18] - 0.

LPIS, bit[17] - ITS and LPI support included.

MBIS, bit[16] - 1.

LSPI, bits[15:11] - 0b00000.

SecurityExtn, bit[10] - Security Support included.

CPUNumber, bits[7:5] - the number of cores in the system, saturated to eight, minus one.

ITLinesNumber, bits[4:0] - the Number of SPIs divided by 32.

[e] The existence of this register depends on the configuration of the GIC-500. If Security Support is not included, this register does not exist.

[f] This register is only accessible from a Secure access.

[g] Writes to bits corresponding to the SGIs are ignored.

[h] GICD_ISENABLER0 is a mixed type register.

[i] GICD_ISENABLER0 SGI bits are RO, PPI bits are RW.

[j] The reset value for the register that contains the SGI and PPI interrupts is 0x0000FFFF because SGIs are always enabled. However, SGIs areGroup 0 on reset, so the reset value for Non-secure reads is 0x00000000.

[k] In configurations where ARE is not programmable, the reset value for SGIs is zero.

[l] The existence of this register depends on the configuration of the GIC-500. If GICv2 backwards compatibility support is not included, this register does not exist.

[m] GICD_ICENABLER0 is a mixed type register.

[n] GICD_ICENABLER0 SGI bits are RO, PPI bits are RW.

[o] The existence of the first of these registers depends on the configuration of the GIC-500. If GICv2 backwards compatibility support is not included, the first register does not exist.

[p] The existence of the first eight of these registers depends on the configuration of the GIC-500. If GICv2 backwards compatibility support is not included, the first eight registers do not exist.

[q] The registers that contain the SGI and PPI interrupts are read-only and the value is the core number of the current access. It is encoded in an 8-bit one-hot field, for each implemented interrupt, and encoded as zero for interrupts that are not implemented. For more information on core target field bit values, see the ARM® Generic Interrupt Controller Architecture Specification version 3.0.

[r] In a system with a single core, these registers are RAZ/WI. For more information, see the ARM® Generic Interrupt Controller Architecture Specification version 3.0.

[s] The even bits of this register are RO. For more information, see the ARM® Generic Interrupt Controller Architecture Specification version 3.0.

[t] The existence of this register depends on the configuration of the GIC-500. If GICv2 backwards compatibility support is not included, this register does not exist.

[u] The value of PIDR0 differs between the GICD, GICR, and GITS versions, and so you can tell the difference between these pages.


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