A.5. AXI4 slave interface signals

The GIC-500 provides a 32-bit wide AXI4 slave interface. See the ARM® AMBA® AXI and ACE Protocol Specification.

AXI4 signals that are not implemented in the GIC-500 are not shown in Table A.5.

Table A.5. The GIC-500 implementation of AXI4 slave signals

AXI signal

Type

Source/destination

GIC-500 implementation

Write address channel signals

awuser_s[variable][a]InputAXI4 interconnect

Non-standard width with respect to the ARM® AMBA® AXI and ACE Protocol Specification.

Bits [2:0] must contain the linear ID of the core performing the write, if backwards compatibility mode is supported. See Topologies and terminology for more information.

Bit [3] indicates a GITS_TRANSLATER write, overriding the awaddr_s, in which the DeviceID comes from awaddr_s[n:2]. If bit[3] is not set and if there is a GITS_TRANSLATER write, the DeviceID comes from the awuser_s[n:4].

awaddr_s[variable][a]

Input

Non-standard width with respect to the ARM® AMBA® AXI and ACE Protocol Specification.

awid_s[variable][a]

Input

Non-standard width with respect to the ARM® AMBA® AXI and ACE Protocol Specification.

awlen_s[7:0]

Input

See the ARM® AMBA® AXI and ACE Protocol Specification.

awsize_s[2:0]

InputNon-standard width with respect to the ARM® AMBA® AXI and ACE Protocol Specification.

awburst_s[1:0]

Input

See the ARM® AMBA® AXI and ACE Protocol Specification.

awprot_s[2:0]

Input

awvalid_s

Input

awready_s

Output

Write data channel signals

 
wstrb_s[3:0]InputAXI4 interconnect

See the ARM® AMBA® AXI and ACE Protocol Specification.

wdata_s[31:0]

Input

wvalid_s

Input

wready_s

Output

Write response channel signals

 

bid_s[variable][a]

Output

AXI4 interconnect

Non-standard width with respect to the ARM® AMBA® AXI and ACE Protocol Specification.

bvalid_s

Output

See the ARM® AMBA® AXI and ACE Protocol Specification.

bready_sInput

bresp_s[1:0]

Output

 
Read address channel signals 

araddr_s[variable][a]

Input

AXI4 interconnect

Non-standard width with respect to the ARM® AMBA® AXI and ACE Protocol Specification.

arid_s[variable][a]

Input

Non-standard width with respect to the ARM® AMBA® AXI and ACE Protocol Specification.

arlen_s[7:0]

Input

See the ARM® AMBA® AXI and ACE Protocol Specification.

arsize_s[2:0]

Input

aruser_s[2:0]

Input

Non-standard width with respect to the ARM® AMBA® AXI and ACE Protocol Specification.

Bits [2:0] must contain the linear ID of the core performing the read, if backwards compatibility mode is supported. See Topologies and terminology for more information.

Bit [3] indicates a GITS_TRANSLATER write, overriding the araddr_s, in which the DeviceID comes from araddr_s[n:2]. If bit[3] is not set, if there is a GITS_TRANSLATER write, the DeviceID comes from the aruser_s[n:4].

arburst_s[1:0]

Input

See the ARM® AMBA® AXI and ACE Protocol Specification.

arprot_s[2:0]

Input

arvalid_s

Input

arready_s

Output

Read data channel signals

rid_s[variable][a]

Output

AXI4 interconnect

Non-standard width with respect to the ARM® AMBA® AXI and ACE Protocol Specification.

rdata_s[31:0]

Output

See the ARM® AMBA® AXI and ACE Protocol Specification.

rresp_s[1:0]

Output

rlast_s

Output

rvalid_s

Output

rready_s

Input

[a] The variable is configuration dependent.


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