2.3.3. Interrupt triggering

The GIC-500 supports two types of physical interrupt signal:

Level-sensitive

The interrupt is pending while the interrupt input is asserted.

Edge-triggered

A rising-edge on the interrupt input causes the interrupt to become pending. The pending bit is later cleared when the interrupt is activated by the CPU interface.

You must program GICD_ICFGRn and, for PPIs using ARE = 1, GICR_ICFGR1, to have the correct settings for the system.

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