ARM® CoreLink™ GIC-500 Generic Interrupt Controller Technical Reference Manual

Revision: r0p0


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the GIC-500
1.1.1. Topologies and terminology
1.2. Compliance
1.3. Features
1.4. Interfaces
1.5. Configurable options
1.6. Test features
1.7. Product documentation
1.8. Product revisions
2. Functional Description
2.1. About the functions
2.2. Interfaces
2.2.1. AXI4 Slave Interface
2.2.2. AXI4 Master Interface
2.2.3. RAM Interfaces
2.2.4. Physical interrupt signals
2.2.5. GIC-500 Stream Protocol Interface
2.2.6. Other core signals
2.3. Operation
2.3.1. Interrupt types
2.3.2. Interrupt groups
2.3.3. Interrupt triggering
2.3.4. Backwards compatibility
2.3.5. Disable Security
2.3.6. Power management
2.4. Clocking and resets
2.5. Constraints and limitations
3. Programmers Model
3.1. About the GIC-500 programmers model
3.2. The GIC-500 register map
3.2.1. Discovery
3.2.2. Effect of Device ID multiplexing
3.2.3. GIC-500 register access and banking
3.3. Distributor register summary
3.4. Distributor register descriptions
3.4.1. Distributor Implementer Identification Register
3.4.2. Peripheral ID2 Register
3.5. Distributor registers for message-based SPIs summary
3.6. Redistributor registers for control and physical LPIs summary
3.7. Redistributor register descriptions
3.7.1. Peripheral ID2 Register
3.8. Redistributor registers for SGIs and PPIs summary
3.9. ITS control register summary
3.10. ITS control register descriptions
3.10.1. ITS Identification Register
3.10.2. Peripheral ID2 Register
3.11. ITS translation register summary
3.12. Implementation defined test registers in GICD page summary
3.12.1. Extended Status Register
3.12.2. Error Test Register
3.12.3. Shared Peripheral Interrupt Status Register
3.13. Implementation defined test registers in the GICR page for PPIs and SGIs
3.13.1. Miscellaneous Status Register
3.13.2. Private Peripheral Interrupt Status Register
3.14. Implementation defined test registers in the GITS control page summary
3.14.1. Tracking Control Register
3.14.2. Tracking Status Register
3.14.3. Debug Tracked DID Register
3.14.4. Debug Tracked PID Register
3.14.5. Debug Tracked ID Register
3.14.6. Debug Tracked Target Register
3.14.7. Debug ITE Cache Statistics
3.14.8. Debug LPI Cache Statistics
A. Signal Descriptions
A.1. Clock and reset signals
A.2. Miscellaneous signals
A.3. Interrupt signals
A.4. Test signals
A.5. AXI4 slave interface signals
A.6. AXI4 master interface signals
A.7. GIC Stream master interfaces
A.8. GIC Stream slave interfaces
A.9. MBIST interface signals
B. Revisions

List of Tables

1. Typographical conventions
1.1. Configurable options for the GIC-500 RTL
2.1. AXI slave interface attributes
2.2. AXI master interface attributes
3.1. Lower half of address map
3.2. Upper half of address map
3.3. Distributor register summary
3.4. GICD_IIDR bit assignments
3.5. GICD_PIDR2 bit assignments
3.6. Distributor registers for message-based SPI register summary
3.7. Redistributor register summary
3.8. GICR_PIDR2 bit assignments
3.9. Redistributor registers for SGIs and PPIs summary
3.10. ITS control register summary
3.11. GITS_IIDR bit assignments
3.12. GITS_PIDR2 bit assignments
3.13. ITS translation register
3.14. Implementation defined test register summary
3.15. GICD_ESTATUSR bit assignments
3.16. GICD_ERRTESTR bit assignments
3.17. GICD_SPISRn bit assignments
3.18. Implementation defined test register summary
3.19. GICR_MISCSTATUSR bit assignments
3.20. GICR_PPISR bit assignments
3.21. Implementation defined test register summary
3.22. GITS_TRKCTRL bit assignments
3.23. GITS_TRKR bit assignments
3.24. GITS_SPISRn bit assignments
3.25. GITS_TRKPIDR bit assignments
3.26. GITS_TRKVIDR bit assignments
3.27. GITS_TRKTGTR bit assignments
3.28. GITS_TRKICR bit assignments
3.29. GITS_TRKLCR bit assignments
A.1. Clock and reset signals
A.2. Miscellaneous signals
A.3. Interrupt signals
A.4. Test signals
A.5. The GIC-500 implementation of AXI4 slave signals
A.6. GIC-500 implementation of AXI4 master signals
A.7. GIC Stream master interfaces
A.8. GIC Stream slave interfaces
A.9. MBIST interface signals
B.1. Issue A
B.2. Differences between issue A and issue B

Proprietary Notice

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Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A 30 April 2014First release for r0p0
Revision B 21 May 2014Second release for r0p0
Copyright © 2014 ARM. All rights reserved.ARM DDI 0516B
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