3.7.4. TBU Performance Interrupt register

The SMMU_ITOP_PERF_INDEX register characteristics are:

Purpose

Enables TBU performance interrupts.

Configuration

Available in all MMU-500 configurations.

Usage constraints

The values of the RAM_MODE and MODULE bits of the SMMU_ITCTRL register define the behavior of this register, as follows:

  • If the SMMU_ITCTRL.RAM_MODE bit is set to 0b0, the register specifies the TBU interrupt information.

  • If the SMMU_ITCTRL.RAM_MODE bit is set to 0b1 and the SMMU_ITCTRL.MODULE bit is set to 0b0, the register specifies TCU RAM information.

  • If the SMMU_ITCTRL.RAM_MODE bit is set to 0b1 and the SMMU_ITCTRL.MODULE bit is set to 0b1, the register specifies TBU RAM information.

Attributes

Figure 3.10 shows the bit assignments when the SMMU_ITCTRL.RAM_MODE bit is set to 0b0.

Figure 3.10. SMMU_ITOP_PERF_INDEX register bit assignments-SMMU_ITCTRL.RAM_MODE0

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Table 3.22 shows the bit assignments when the SMMU_ITCTRL.RAM_MODE bit is set to 0b0.

Table 3.22. SMMU_ITOP_PERF_INDEX register bit assignments-SMMU_ITCTRL.RAM_MODE0

BitsName Reset valueDescription
[31:0]TBUINT-

TBU interrupt to enable. This bit field can have one of the following values:

0

Enable performance interrupt for TBU 0.

1

Enable performance interrupt for TBU 1.

...

...

31

Enable performance interrupt for TBU 31.

Note

You must specify values only for existing TBUs.


Figure 3.11 shows the bit assignments when the SMMU_ITCTRL.RAM_MODE bit is set to 0b1 and the SMMU_ITCTRL.MODULE bit is set to 0b0 to specify TCU RAMs.

Figure 3.11. SMMU_ITOP_PERF_INDEX register bit assignments-SMMU_ITCTRL.RAM_MODE1.MODULE0

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Table 3.23 shows the bit assignments when the SMMU_ITCTRL.RAM_MODE bit is set to 0b1 and the SMMU_ITCTRL.MODULE bit is set to 0b0 to specify TCU RAMs.

Table 3.23. SMMU_ITOP_PERF_INDEX register bit assignments-SMMU_ITCTRL.RAM_MODE1.MODULE0

BitsName Reset valueDescription
[31:30]WAY_IPA2PA_PF-

The way in which to read or write the IPA to PA translation prefetch RAM. This bit field can have one of the following values:

0b00

Way 0.

0b01

Way 1.

0b10

Way 2.

0b11

Way 3.

[29:23]Reserved-Reserved.
[22:16]IPA2PA_PF_INDEX-The index of the IPA to PA translation prefetch RAM. The number of valid bits depends on the size of the IPA to PA translation cache or the prefetch cache.
[14:15]WAY_MTLB_WC-

The way in which to read or write the MTLB_WC RAM. This bit field can have one of the following values:

0b00

Way 0.

0b01

Way 1.

0b10

Way 2.

0b11

Way 3.

[12:13]Reserved-Reserved.
[11:0]MTLB_WC_INDEX-The index of the MTLB_WC RAM. The number of valid bits depends on the size of the macro-TLB and the PTW cache.

Figure 3.11 shows the bit assignments when the SMMU_ITCTRL.RAM_MODE bit is set to 0b1 and the SMMU_ITCTRL.MODULE bit is set to 0b1 to specify TBU RAMs.

Figure 3.12. SMMU_ITOP_PERF_INDEX register bit assignments-SMMU_ITCTRL.RAM_MODE1.MODULE1

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Table 3.23 shows the bit assignments when the SMMU_ITCTRL.RAM_MODE bit is set to 0b1 and the SMMU_ITCTRL.MODULE bit is set to 0b1 to specify TBU RAMs.

Table 3.24. SMMU_ITOP_PERF_INDEX register bit assignments-SMMU_ITCTRL.RAM_MODE1.MODULE1

BitsName Reset valueDescription
[31:7]Reserved-Reserved.
[6:0]TLB_RAM_INDEX-The TLB RAM index.

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