3.8.2. Peripheral Identification registers

The characteristics of the PeriphID registers are:

Purpose

Bits[7:0] of the PeriphID 0-4 registers are used and bits[31:8] are Reserved. The PeriphID 7-5 registers are Reserved.

Configuration

Available in all MMU-500 configurations.

Usage constraints

There are no usage constraints.

Attributes

The peripheral identification registers are as follows:

Peripheral Identification register 0

Figure 3.18 shows the bit assignments.

Figure 3.18. PeriphID0 register bit assignments

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Table 3.30 shows the bit assignments.

Table 3.30. PeriphID0 register bit assignments

BitsNameReset valueDescription
[31:8]Reserved-Reserved.
[7:0]PartNumber00x81Middle and lower-packed BCD value of the device number [7:0].

Peripheral Identification register 1

Figure 3.19 shows the bit assignments.

Figure 3.19. PeriphID1 register bit assignments

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Table 3.31 shows the bit assignments.

Table 3.31. PeriphID1 register bit assignments

BitsNameReset valueDescription
[31:8]Reserved-Reserved.
[7:4]JEP106 identity code0xBJEP106 identity code.
[3:0]PartNumber10x4Upper packed-BCD value of the device number [11:8].

Peripheral Identification register 2

Figure 3.20 shows the bit assignments.

Figure 3.20. PeriphID2 register bit assignments

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Table 3.32 shows the bit assignments.

Table 3.32. PeriphID2 register bit assignments

BitsNameReset valueDescription
[31:8]Reserved-Reserved.
[7:4]Revision0x0Revision number of the peripheral, which starts from 0x0.
[3]JEDEC0x1Always set, indicates that a JEDEC-assigned value is used.
[2:0]JEP106 identity code0x3JEP106 continuation code, which identifies the designer. The value of 0x3 indicates ARM.

Peripheral Identification register 3

Figure 3.21 shows the bit assignments.

Figure 3.21. PeriphID3 register bit assignments

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Table 3.33 shows the bit assignments.

Table 3.33. PeriphID3 register bit assignments

BitsName Reset valueDescription
[31:8]Reserved-Reserved.
[7:4]RevAnd0x0Manufacturer revision number. By default, this value is set to 0x0 (specified by ARM).
[3:0]Customer modified0x0Customer modified number.This value is set to 0x0 (specified by ARM).

Peripheral Identification register 4

Figure 3.22 shows the bit assignments.

Figure 3.22. PeriphID4 register bit assignments

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Table 3.34 shows the bit assignments.

Table 3.34. PeriphID4 register bit assignments

BitsNameReset valueDescription
[31:8]Reserved-Reserved.
[7:4]4KB Count

1-8 contexts: 0x8

9-16 contexts: 0x9

17-32 contexts: 0xA

33-64 contexts: 0xB

Indicates the log_base_2Number of 4KB blocks occupied by the interface value. The reset value varies with the number of configured contexts.
[3:0]JEP106 continuation code0x4JEP106 continuation code, which identifies the designer. The value of 0x4 indicates ARM.

Peripheral Identification registers 5-7

Figure 3.23 shows the bit assignments.

Figure 3.23. PeriphID5-7 register bit assignments

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Table 3.35 shows the bit assignments.

Table 3.35. PeriphID5-7 register bit assignments

BitsName Reset valueDescription
[31:0]Reserved-Reserved

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