3.3. Memory model

The address map of the programming interface is consistent with the ARM® System Memory Management Unit Architecture Specification.

In addition to the registers specified in the ARM® System Memory Management Unit Architecture Specification, the MMU-500 implements the following configuration, identification, debug, context, integration, performance, and control registers:

The MMU-500 does not support the following Global Space Invalidation registers for stage 2 configurations:


The SMMU_SCR1.NSNUMCBO bit field is RO for Only stage 2 translations configurations.

The MMU-500 is configured through a memory-mapped register frame. The total size of the MMU-500 address range depends on the number of implemented translation contexts.

The MMU-500 address map consists of the following equally-sized regions:

The global address space

The global address space is located at the bottom of the MMU-500 address space, at SMMU_BASE. See Figure 3.1.

The translation context bank address space

The translation context bank address space is located above the top of the global address space, at SMMU_TOP. See Figure 3.1.

Figure 3.1. MMU-500 address map

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You can determine the MMU-500 address range by reading the value of the following register fields:

See the ARM® System Memory Management Unit Architecture Specification for more information.

You can program the context page size as 4KB or 64KB using the SMMU_SACR.PAGESIZE bit. This bit can only be programmed on reset, and can be re-programmed only when the MMU-500 is inactive.


The MMU-500 ignores non-word aligned write accesses to any of the registers.

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