1.1. About the MMU-500

The MMU-500 is a system-level Memory Management Unit (MMU), that translates an input address to an output address, by performing one or more translation table walks.

It supports the translation table formats defined by the ARM architecture, ARMv7 and ARMv8, and can perform:

A single stage of address translation requires a single translation table walk. This walk often requires multiple translation table lookups, that are called the levels of lookup.

In addition to translating an input address to an output address, a stage of address translation also defines the memory attributes of the output address. With a two-stage translation, the stage 2 translation can modify the attributes defined by the stage 1 translation.

A stage of address translation can be disabled, or bypassed, and the MMU-500 can define memory attributes for a bypassed stage of translation.

The MMU recognizes independent Secure and Non-secure translation contexts. A translation context provides information and resources required by the MMU-500 to process a transaction.

For the stage 1 translations that are typically associated with application and Operating System (OS) level operation, the VA range can be split into two subranges, each with associated translation tables and control registers.

These features mean the MMU-500 can perform all of the address translations defined by the ARMv7 and ARMv8 architectures, for memory accesses from either AArch32 state or from AArch64 state.

Stage 1 translations are supported for both Secure and Non-secure translation contexts. Usually, the appropriate OS:

Stage 2 translations are supported only for Non-secure translation contexts. For Non-secure processor operation, the typical usage model for two stages of address translation is as follows:

The MMU-500 can cache the result of a translation table lookup in a Translation Lookaside Buffer (TLB). This means the MMU-500 also supports TLB maintenance operations.

For more information about:

The MMU-500 has the following key components:

Translation Buffer Unit (TBU)

The TBU contains a Translation Look-aside Buffer (TLB) that caches page tables. The MMU-500 implements a TBU for each connected master, and a TBU can be implemented so that it is local to the master rather than local to the MMU-500.

Translation Control Unit (TCU)

Controls and manages the address translations. The MMU-500 implements a single TCU.

Interconnect

Connects the multiple TBUs to the TCU.

Figure 1.1 shows the block diagram for MMU-500.

Figure 1.1. MMU-500 block diagram

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See Chapter 2 Functional Description for more information about logical processing steps, interfaces, and operational features.

The following are example masters for the MMU-500:

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