A.3. Low-power interface signals

Table A.14 shows the standard TCU LPI signals.

Table A.14. TCU LPI signals

LPI signalTCU block signalWidthDirection
QREQnqreqn_tcu1I
QACTIVEqactive_tcu1O
QACCEPTnqacceptn_tcu1O

Table A.15 shows the standard TBU LPI signals.

Table A.15. TBU LPI signals

LPI signalTBU block signalWidthDirection
QREQnqreqn_tbu_<tbuname>_pd1I
qreqn_tbu_<tbuname>_cg1
qreqn_pd_slv_br_<tbuname>1
qreqn_pd_mst_br_<tbuname>1
QACCEPTnqacceptn_tbu_<tbuname>_pd1O
qacceptn_tbu_<tbuname>_cg1
qacceptn_pd_slv_br_<tbuname>1
qacceptn_pd_mst_br_<tbuname>1
QACTIVEqactive_tbu_<tbuname>_cg1O
qactive_br_tbu_<tbuname>1

qactive_br_tcu_<tbuname>

1

Table A.16 shows the awakeup signals. See the ARM® CoreLink™ MMU-500 System Memory Management Unit Integration Manual for more information.

The MMU-500 ensures that the awakeup signal outputs are driven from a flip-flop and along with a transaction axvalid, or for multiplexed configurations the awakeup signal can be delayed by one cycle with respect to an asserted axvalid to ensure it is a registered output.

Table A.16. awakeup signals

SignalWidthI/ODescriptionBlock
awakeup_<tbuname>_s1IIndicates that one of address read, address write, or write data channels have active transactions pending at the TBU slave interface.TBU
awakeup_<tbuname>_m1OIndicates that one of address read, address write, or write data channels have active transactions pending at the TBU master interfaceTBU
awakeup_ptw1OIndicates that a PTW transaction is present at the TCU master interface. This signal is present only when you specify a dedicated PTW channel.TCU
awakeup_dvm_ptw1IIndicates that a DVM transaction is present on the TCU AC channel. This signal is present only when you specify a dedicated PTW channel.TCU
awakeup_dvm_<tbuname>1IIndicates that a DVM transaction is present on the TBU AC channel. This signal is present only when you do not specify a dedicated PTW channel.TBU
awakeup_prog1IIndicates that one of address read, address write, or write data channels have active transactions pending at the TCU programming interface.TCU

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