A.4.4. Tie-off signals

Table A.20 shows the tie-off signals.

Table A.20. Tie-off signals

SignalI/OWidthDescription
cfg_cttwI1Static configuration to indicate whether the MMU-500 performs coherent PTWs. This signal cannot change after reset.
dftclkenableI1

When this signal is HIGH, the MMU-500 bypasses architectural clock gates. This signal is used in the DFT test mode. You can specify one of the following values:

0b0

Functional mode.

0b1

Bypass architectural clock gates in the DFT test mode.

integ_sec_overrideI1When this signal is set, Non-secure accesses can access the integration registers. See Integration registers.
sysbardisable_<tbuname>I0Indicates that the master or slave connected to the MMU-500 is the AXI3 interface. It is assumed that no barriers are generated at input or output.

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