2.4.2. Macro TLB

The macro TLB caches PTW results in the TCU. You can configure the depth of the macro TLB based on your requirements.

Figure 2.6 show the TCU cache structure, which consists of macro TLBs, Prefetch buffers, and PTW caches.

Figure 2.6. TCU cache

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See the ARM® CoreLink™ MMU-500 System Memory Management Unit Supplement to AMBA® Designer (ADR-400) User Guide for more information on the TCU configurability.

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