ARM® CoreLink™ MMU-500 System Memory Management Unit Technical Reference Manual

Revision: r0p0

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback on this product
Feedback on content
1. Introduction
1.1. About the MMU-500
1.1.1. MMU-500 example system
1.2. Compliance
1.3. Features
1.4. Interfaces
1.5. Configurable options
1.5.1. Output ID width
1.6. Product documentation and design flow
1.6.1. Documentation
1.7. Test features
1.8. Product revisions
2. Functional Description
2.1. About the functions
2.2. Interfaces
2.2.1. TCU interfaces
2.2.2. TBU interfaces
2.2.3. Common interfaces
2.3. Operation
2.3.1. Stream ID
2.3.2. Security determination
2.3.3. Hit-Under-Miss
2.3.4. Fault handling
2.3.5. Implementation defined operational features
2.4. Cache structures of the MMU-500
2.4.1. Micro TLB
2.4.2. Macro TLB
2.4.3. Prefetch buffer
2.4.4. Page table walk cache
2.4.5. IPA to PA cache
2.5. Constraints and limitations of use
2.5.1. AXI3 and AXI4 support
2.5.2. Restrictions for configuration parameters
3. Programmers Model
3.1. About this programmers model
3.1.1. Dynamic programming
3.2. Modes of operation and execution
3.3. Memory model
3.3.1. Reset values
3.4. Register summary
3.4.1. Global address space 0 registers summary
3.4.2. Translation context bank registers summary
3.4.3. Integration registers summary
3.4.4. Peripheral and component identification registers summary
3.5. Global address space 0
3.5.1. Auxiliary Configuration registers
3.5.2. Debug registers
3.6. Translation context address space
3.6.1. Auxiliary Control registers
3.7. Integration registers
3.7.1. Integration Mode Control Register
3.7.2. Integration Test Input register
3.7.3. Integration Test Output Global register
3.7.4. TBU Performance Interrupt register
3.7.5. Integration Test Ouptut Context Interrupt registers
3.7.6. TBU QoS registers
3.7.7. Parity Error Checker Register
3.8. Peripheral and component identification registers
3.8.1. Component Identification registers
3.8.2. Peripheral Identification registers
A. Signal Descriptions
A.1. Clock and resets
A.2. ACE-Lite signals
A.2.1. Write address channel signals
A.2.2. Write data channel signals
A.2.3. Write response channel signals
A.2.4. Read address channel signals
A.2.5. Read data channel signals
A.2.6. Snoop channel signals
A.3. Low-power interface signals
A.4. Miscellaneous signals
A.4.1. Sideband signals
A.4.2. Interrupt signals
A.4.3. Authentication interface signal
A.4.4. Tie-off signals
A.4.5. Performance event signals
B. Revisions

List of Tables

1. Typographical conventions
1.1. Configurable options
3.1. Reset values of SMMU_IDR registers, both Secure and Non-secure
3.2. Reset values of Performance Monitor Extension registers
3.3. Global space 0 registers summary
3.4. Translation context registers summary
3.5. Integration registers summary
3.6. Peripheral and component identification summary
3.7. SMMU_ACR Register bit assignments
3.8. SMMU_sACR Register bit assignments
3.9. SMMU_DBGRPTRTBU register bit assignments
3.10. SMMU_DBGRPTRTCU register bit assignments
3.11. Debug read data register data format, word 0
3.12. Debug read data register data format, word 1
3.13. Debug read data register data format, word 2
3.14. Debug read data register data format, word 3
3.15. Debug read data register data format, word 4
3.16. Debug read data register data format, word 5
3.17. Debug read data register data format, word 6
3.18. SMMU_CBn_ACTLR Registers bit assignments
3.19. SMMU_ITCTRL register bit assignments
3.20. SMMU_ITIP register bit assignments
3.21. SMMU_ITOP_GLBL register bit assignments
3.22. SMMU_ITOP_PERF_INDEX register bit assignments-SMMU_ITCTRL.RAM_MODE0
3.23. SMMU_ITOP_PERF_INDEX register bit assignments-SMMU_ITCTRL.RAM_MODE1.MODULE0
3.24. SMMU_ITOP_PERF_INDEX register bit assignments-SMMU_ITCTRL.RAM_MODE1.MODULE1
3.25. SMMU_ITOP_CXTnTOm_RAMx registers bit assignments-SMMU_ITCTRL.RAM_MODE0
3.26. SMMU_ITOP_CXTnTOm_RAMx registers bit assignments-SMMU_ITCTRL.RAM_MODE1
3.27. SMMU_TBUQOSx registers bit assignments
3.28. SMMU_PER Register bit assignments
3.29. CID0-3 registers bit assignments
3.30. PeriphID0 register bit assignments
3.31. PeriphID1 register bit assignments
3.32. PeriphID2 register bit assignments
3.33. PeriphID3 register bit assignments
3.34. PeriphID4 register bit assignments
3.35. PeriphID5-7 register bit assignments
A.1. TCU clock and reset signals
A.2. TBU clock and reset signals
A.3. TBU write address channel signals
A.4. TCU write address channel signals
A.5. TBU write data channel signals
A.6. TCU write data channel signals
A.7. TBU write response channel signals
A.8. TCU write response channel signals
A.9. TBU read address channel signals
A.10. TCU read address channel signals
A.11. TBU read data channel signals
A.12. TCU read data channel signals
A.13. Snoop channel signals
A.14. TCU LPI signals
A.15. TBU LPI signals
A.16. awakeup signals
A.17. Sideband signals
A.18. Interrupt signals
A.19. Authentication Interface signal
A.20. Tie-off signals
A.21. Performance event signals
B.1. Issue A

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Confidentiality Status

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Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A22 August 2013First release for r0p0
Copyright © 2013 ARM. All rights reserved.ARM DDI 0517A