3.7.1. Auxiliary Control registers

The SMMU_CBn_ACTLR characteristics are:


Enable context caching in the macro TLB or prefetch buffer.


Available in all MMU-500 configurations.

Usage constraints

You must modify this register only during the MMU-500 initialization, otherwise the register modification invalidates all TCU caches.


You can modify this register only when the ACR.CACHE_LOCK bit is 0.


Figure 3.6 shows the bit assignments.

Figure 3.6. SMMU_CBn_ACTLR registers bit assignments

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Table 3.18 shows the bit assignments.

Table 3.18. SMMU_CBn_ACTLR registers bit assignments

BitsName Reset valueDescription
[1]CPRE0b1Enable context caching in the prefetch buffer.
[0]CMTLB0b1Enable context caching in the macro TLB.

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