3.5.1. Auxiliary Configuration registers

The SMMU_ACR and SMMU_sACR characteristics are:

Purpose

The Auxiliary Configuration registers, SMMU_ACR (Non-secure) and SMMU_sACR (Secure), are defined as shown in Table 3.7 and Table 3.8 respectively.

Configuration

Available in all MMU-500 configurations.

Usage constraints

The S2WC2EN bit is Non-secure only. Other bits are banked with security.

Attributes

Figure 3.2 shows the bit assignments.

Figure 3.2. SMMU_ACR register bit assignments

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Table 3.7 shows the bit assignments.

Table 3.7. SMMU_ACR register bit assignments

BitsNameReset valueDescription
[31:27]Reserved-Reserved.
[26]CACHE_LOCK0b1

Locks the write access to the SMMU_CBn_ACTLR.

The SMMU_ACR.CACHE_LOCK bit can have one of the following values:

0b0

The SMMU_CBn_ACTLR in all Non-secure contexts is R/W.

0b1

The SMMU_CBn_ACTLR in all Non-secure contexts is RO.

[25]DP4K_TBUDISB0b0

4KB page size dependency check. Enables or disables the 4KB page size dependency check in the TBU.

Transactions form a dependency on a transaction that is already performing the PTW. The preconditions are that they are within the same 4KB address space and have the same StreamID and security state as the transaction performing the PTW. This is the default behavior that you can change by programming the bits to not set the dependency. This results in extra latencies and power consumption, and is intended only for debug purposes.

This bit resets to zero. When it is set to one, the 4KB dependency check in the TBU is disabled.

[24]DP4K_TCUDISB0b0

4KB page size dependency check. Enables or disables the 4KB page size dependency check in the TCU.

This bit resets to zero. When it is set to one, the 4KB dependency check in the TCU is disabled.

[23:11]Reserved-Reserved.
[10]S2CRB_TLBEN0b0

Stream-to-context register bypass TLB enable. This bit can have one of the following values:

0b0

Do not update the TLB with the stream-to-context register bypass transaction information.

0b1

Update the TLB with the stream-to-context register bypass transaction information.

Note

For the S2CRB_TLBEN, MMUDISB_TLBEN, and SMTNMB_TLBEN bits, the bypass TLB enable bits ensure that the latency is minimal for additional transactions that must undergo the same bypass. However, this comes with the penalty of a TLB entry being occupied for the bypass entry that reduces the effective depth of the TLB available for caching translation operations.

[9]MMUDISB_TLBEN0b0

MMU disable bypass TLB enable.

The MMU-500 caches in the TLB the attribute information for transactions that have been allocated a context, but the SMMU_CBn_SCTLR.M bit is set to 0b0 for the context.

This caching reduces the transaction time by six clock cycles, but can save much more, depending on how busy the MMU-500 is.

This bit can have one of the following values:

0b0

Do not update the TLB with the MMU disable transaction information.

0b1

Update the TLB with the MMU disable transaction information.

[8]SMTNMB_TLBEN0b0

Stream match table no match TLB enable. This bit can have one of the following values:

0b0

Do not update the TLB with the stream match table no match TLB enable bypass transaction information.

0b1

Update the TLB with the stream match table no match TLB enable bypass transaction information.

[7:5]Reserved-Reserved.
[4]IPA2PA_CEN0b1

IPA to PA cache enable. This bit can have one of the following values:

0b0

Disable the IPA to PA cache.

0b1

Enable the IPA to PA cache.

Note

This bit is reserved when the Only stage 2 translations option is enabled.

[3]S2WC2EN0b1

Stage 2 PTW cache 2 enable.

The MMU-500 caches the level 2 PTWs in the stage 2 PTW cache 2.

This bit can have one of the following values:

0b0

Disable the PTW cache 2.

0b1

Enable the PTW cache 2.

[2]S1WC2EN0b1

Stage 1 PTW cache 2 enable.

The MMU-500 caches the level 2 PTW in the stage 1 PTW cache 2.

This bit can have one of the following values:

0b0

Disable the PTW cache 2.

0b1

Enable the PTW cache 2.

[1:0]Reserved-Reserved.

Figure 3.3 shows the bit assignments.

Figure 3.3. SMMU_sACR register bit assignments

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Table 3.8 shows the bit assignments.

Table 3.8. SMMU_sACR register bit assignments

BitsNameReset valueDescription
[31:27]Reserved-Reserved.
[26]CACHE_LOCK0b1

Locks the write access to the SMMU_CBn_ACTLR.

The SMMU_sACR.CACHE_LOCK bit can have one of the following values:

0b0

The SMMU_CBn_ACTLR in all Secure contexts is R/W and Non-secure contexts follows SMMU_ACR.CACHE_LOCK.

0b1

The SMMU_CBn_ACTLR in all contexts is RO.

[25:17]Reserved-Reserved.
[16]PAGESIZE0b0

SMMU Page Size.

An SMMU register map arranges state into a number of pages. Each page occupies, and is aligned to, a PAGESIZE space in the address map. Such organization permits a hypervisor to permit or deny access to system MMU state on a page-by-page basis.The SMMU architecture permits an implementation to support either 4KB or 64KB PAGESIZE options.

This bit can have one of the following values:

0b0

4KB.

0b1

64KB.

[15:11]Reserved-Reserved.
[10]S2CRB_TLBEN0b0

Stream to context register bypass TLB enable. This bit can have one of the following values:

0b0

Do not update the TLB with the stream to context register bypass transaction information.

0b1

Update the TLB with the stream to context register bypass transaction information.

[9]MMUDISB_TLBEN0b0

MMU disable bypass TLB enable.

The MMU-500 caches in the TLB the attribute information for transactions that have been allocated a context, but the SMMU_CBn_SCTLR.M bit is set to 0b0 for the context.

This caching reduces the transaction time by six clock cycles, but could save much more, depending on how busy the MMU-500 is.

This bit can have one of the following values:

0b0

Do not update the TLB with the MMU disable transaction information.

0b1

Update the TLB with the MMU disable transaction information.

[8]SMTNMB_TLBEN0b0

Stream match table no match TLB enable. This bit can have one of the following values:

0b0

Do not update the TLB with the stream match table no match TLB enable bypass transaction information.

0b1

Update the TLB with the stream match table no match TLB enable bypass transaction information.

[7:3]Reserved-Reserved.
[2]S1WC2EN0b1

Stage 1 walk cache 2 enable. The MMU-500 caches the level 2 PTWs in the stage 1 PTW cache 2.

You can enable or disable this behavior by using the SMMU_ACR.S1WC2EN bit.

This bit can have one of the following values:

0b0

Disable the PTW cache 2.

0b1

Enable the PTW cache 2.

[1:0]Reserved-

Reserved.


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