3.8.1. Integration Mode Control Register

The SMMU_ITCTRL register characteristics are:

Purpose

This register enables the component to switch from functional mode to integration mode. You can directly control the inputs and outputs in integration mode.

Note

A device might not operate with the original behavior in integration mode.

After performing integration, you must reset the system to ensure the correct behavior of system components that are affected by the integration.

Writing to this register other than when in the disabled state results in Unpredictable behavior.

Configuration

Available in all MMU-500 configurations.

Attributes

Figure 3.7 shows the bit assignments.

Figure 3.7. SMMU_ITCTRL register bit assignments

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Table 3.19 shows the bit assignments.

Table 3.19. SMMU_ITCTRL register bit assignments

BitsName Reset valueDescription
[31:9]Reserved-Reserved.
[8:4]ACCESS-

Specifies the access information. The functionality of this bit field is determined by the value of the SMMU_ITCTRL.MODULE bit.

If the SMMU_ITCTRL.MODULE bit is set to 0b0, the SMMU_ITCTRL bits[8:5] are ignored, and the SMMU_ITCTRL bit[4] field can have one of the following values:

0b00

IPA2PA access. The MMU-500 sets the RAM mode, and accesses it in the direction specified by the value of the RAM WNR bit.

0b01

MTLB_WC RAM access. The MMU-500 sets the RAM mode and accesses it in the direction specified by the RAM WNR bit.

0b10

CD MFIFO RAM access. The MMU-500 sets the RAM mode and accesses it in the direction specified by the RAM WNR bit.

If the SMMU_ITCTRL.MODULE bit is set to 0b1 (that is, the TBU RAM is specified), this bit field provides the TBU number from which the RAM must read or write. Only log2(Number of TBUs) bits are valid.

[3]MODULE-

The TBU or TCU RAM. This bit can have one of the following values:

0b0

TCU RAM. Bit[4] provides the TCU RAM information.

0b1

TBU RAM. Bit[4] provides the TBU RAM information.

[2]RAM_DATA-

RAM data WNR. This bit can have one of the following values:

0b0

The MMU-500 reads from the RAM with the index specified in the SMMU_ITOP_PERF_INDEX register.

0b1

The MMU-500 writes to the RAM with the index specified in the SMMU_ITOP_PERF_INDEX register.

[1]RAM_MODE0b0

RAM mode. This bit can have one of the following values:

0b0

The MMU-500 does not drive the RAM bus or read from the RAM.

0b1

The MMU-500 drives the RAM bus or reads from the RAM.

[0]INTGMODE0b0

Integration Mode. Enables the component to switch between functional mode and integration mode. This bit can have one of the following values:

0b0

Disable integration mode.

0b1

Enable integration mode.


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