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Home > Introduction > Configurable options |
The MMU-500 implementer can configure the following options:
TCU Options
Number of configurable TBUs
Number of TBUs
Stream ID - width of the sideband signal
AXI ID signal width of the programming
interface
PTW has a separate AXI port
PTW AXI data bus width
Only stage 2 translations
Number of contexts
Number of SMR groups
Walk caches depth
Macro TLB depth
PTW depth
TCU half clock
TBUn Mapping
Instance u_tbun
TBU CFGn Options
Name
AXI ID signal width
AXI data bus width
Depth of the write buffer
TLB depth
TBU queue depth
Implement the TLB using a memory
Width of the AXI slave interface AWUSER
signals
Width of the AXI slave interface WUSER
signals
Width of the AXI slave interface BUSER
signals
Width of the AXI slave interface ARUSER
signals
Width of the AXI slave interface RUSER
signals
TBU in a separate clock and power domain
Depth of the asynchronous fifo buffer
on the TCU to the TBU channel
Serial data bus width
SSD index signal width
Number of stages for synchronization
Specify use of SSDIndex0-7
Specify SSDIndex0-7
TBU CFGn Timing
AW channel slave interface registering
options
W channel slave interface registering
options
B channel slave interface registering
options
AR channel slave interface registering
options
R channel slave interface registering
options
TBU-TCU channel pre-bridge register slice
1 options
TBU-TCU channel pre-bridge register slice
2 options
TBU-TCU channel post-bridge register
slice 1 options
TBU-TCU channel post-bridge register
slice 2 options
TCU-TBU channel pre-bridge register slice
1 options
TCU-TBU channel pre-bridge register slice
2 options
TCU-TBU channel post-bridge register
slice 1 options
TCU-TBU channel post-bridge register
slice 2 options
For more information about the values and descriptions of the configurable options, see the ARM® CoreLink™ MMU-500 System Memory Management Unit Supplement to AMBA® Designer (ADR-400) User Guide.