1.1. About the MMU-500

The MMU-500 is a system-level Memory Management Unit (MMU) that translates an input address to an output address, based on address mapping and memory attribute information available in the MMU-500 internal registers and translation tables.

An address translation from an input address to an output address is described as a stage of address translation.

The MMU-500 supports the translation table formats defined by the ARM architecture, ARMv7 and ARMv8, and can perform:

Address translation can span over two stages, namely stage 1 and stage 2. Address translation can require multiple translation table lookups. Each translation table lookup is described as a level of address lookup. Each level of stage 1 translation might require additional stage 2 translation.

In addition to translating an input address to an output address, a stage of address translation also defines the memory attributes of the output address. With a two-stage translation, the stage 2 translation can modify the attributes defined by the stage 1 translation.

A stage of address translation can be disabled or bypassed, and the MMU-500 can define memory attributes for disabled and bypassed stages of translation.

The MMU-500 uses inputs from the requesting master to identify a context. This context tells the MMU-500 what resources to use for the translation including which translation tables to use.

For the stage 1 translations that are typically associated with application and OS-level operation, the VA range can be split into two subranges, translated by Translation Table Base registers, TTBR0 and TTBR1, each with associated translation tables and control registers.

These features mean the MMU-500 can perform address translations with the following page size limitations, for memory accesses from either AArch32 state or from AArch64 state:

ARMv7 architecture

The MMU-500 supports all page sizes.

ARMv8 architecture

Apart from the 16KB page granule, the MMU-500 supports all page sizes.

Stage 1 translations are supported for both Secure and Non-secure translation contexts. Usually, the appropriate OS:

Stage 2 translations are supported only for Non-secure translation contexts. The typical usage model for two stages of address translation is as follows:

The MMU-500 can cache the result of a translation table lookup in a translation lookaside buffer (TLB) that means the MMU-500 also supports TLB maintenance operations.

For more information about:

The MMU-500 has the following key components:

Translation buffer unit (TBU)

The TBU contains a TLB that caches page tables. The MMU-500 implements a TBU for each connected master, and the TBU is designed, so that it is local to the master.

Translation control unit (TCU)

Controls and manages the address translations. The MMU-500 implements a single TCU.


Connects multiple TBUs to the TCU.

Figure 1.1 shows the MMU-500 block diagram.

Figure 1.1. MMU-500 block diagram

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

For more information about logical processing steps, interfaces, and operational features, see Chapter 2 Functional Description.

The following are example masters for the MMU-500:

Copyright © 2013, 2014 ARM. All rights reserved.ARM DDI 0517C