Appendix B. Revisions

This appendix describes the technical changes between released issues of this book.

Table B.1. Issue A

ChangeLocationAffects
No changes, first release--

Table B.2. Differences between Issue A and Issue B

ChangeLocationAffects
Information added on TBU queue depth support

Chapter 1 Introduction

Chapter 2 Functional Description

r1p0
Information added on 128 contexts support Chapter 1 Introductionr1p0
Information added on support for configuring TCU core to run at half the clock speed compared to TCU external interfaces

Chapter 1 Introduction

Chapter 2 Functional Description

r1p0
Modified page size values for S1 and S2 translationChapter 3 Programmers ModelAll
Information added on Global address space 1 Chapter 3 Programmers ModelAll
Added the dftmcphold signal to Table A.20Appendix A Signal DescriptionsAll
Information added on Peripheral and component identification registers summary. Chapter 3 Programmers ModelAll
Information added on TCU and TBU interfaces

Chapter 1 Introduction

Chapter 2 Functional Description

All
Corrected the clock and power domains in Figure 2.4Chapter 2 Functional DescriptionAll
Information added on TBU barrier supportChapter 2 Functional DescriptionAll
Added SMMU_TBU_PWR_STATUS register to Integration registersChapter 3 Programmers ModelAll

Table B.3. Differences between issue B and issue C

ChangeLocationAffects

Information added on the following:

  • Support for 256 outstanding transactions for each TBU master interface.

  • Support for priority elevation as part of QoS scheme.

Chapter 1 Introductionr2p0
Information added on the dftmchold signal in Test featuresChapter 1 IntroductionAll
Information added on Programming interfaceChapter 2 Functional DescriptionAll
Information added on Low-power interface for clock gating and power controlChapter 2 Functional DescriptionAll

Added StreamID configuration information on the following sections:

Chapter 2 Functional Description

Chapter 3 Programmers Model

Appendix A Signal Descriptions

r2p0
Added information on AXI3 and AXI4 supportChapter 2 Functional DescriptionAll
Added illustrations on StreamIDChapter 2 Functional DescriptionAll
Added information on Modes of operation and executionChapter 3 Programmers ModelAll
Added new registers in Table 3.2
Added information on Performance monitoring
Added new register bit in Auxiliary Configuration registers
Added usage constraint for Auxiliary Control registers
Updated information on Peripheral and component identification registers summary
Updated information on Peripheral Identification register 2
Updated information on Peripheral Identification register 4

Updated information on the following sections:

Appendix A Signal DescriptionsAll

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