A.4.2. Interrupt signals

Table A.18 shows the interrupt signals generated by the MMU-500. See the ARM® System Memory Management Unit Architecture Specification for more information.

Table A.18. Interrupt signals

SignalI/OWidthDescription
gbl_flt_irpt_sO1Global Secure fault interrupt. This interrupt can be cleared by writing 0xFFFFFFFF to a Secure Global Fault Status register.
gbl_flt_irpt_nsO1 Global Non-secure fault interrupt. This interrupt can be cleared by writing 0xFFFFFFFF to a Non-Secure Global Fault Status register.
perf_irpt_<tbuname>O1 Performance counter interrupt, one for every TBU. This interrupt can be cleared by writing one to the corresponding bit in overflowing performance counter, PMOVSCLRx.
cxt_irpt_<SMMU_IDR1.NUMCB-1:0>O1Non-secure context interrupts for 0-(NUM_CONTEXT - 1), where NUM_CONTEXT is the number of contexts. This interrupt can be cleared by writing 0xFFFF_FFFF to a Fault status register, of the faulting context, followed by a write to a Resume register for contexts in stalled status.
comb_irpt_nsO1Non-secure combined interrupt. This combined interrupt is the logical OR of gbl_flt_irpt_ns, perf_irpt_<tbuname>, and cxt_irpt_[(SCR1.NSNUMCBO-1):0].
comb_irpt_sO1Secure combined interrupt. This combined interrupt is the logical OR of gbl_flt_irpt_s and cxt_irpt_[(SMMU_IDR1.NUMCB-1): (SMMU_SCR1.NSNUMCBO].

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