A.2.4. Read address channel signals

Table A.9 shows the ACE-Lite read address channel signals for the TBU.

Table A.9. TBU read address channel signals

ACE-LiteTBU slave portWidthI/OTBU master portWidthI/O
ARIDarid_<tbuname>_sSIW[a]Iarid_<tbuname>_mMIW[b]O
ARADDRaraddr_<tbuname>_s49Iaraddr_<tbuname>_m48O
ARLENarlen_<tbuname>_s8Iarlen_<tbuname>_m8O
ARSIZEarsize_<tbuname>_s3Iarsize_<tbuname>_m3O
ARBURSTarburst_<tbuname>_s2Iarburst_<tbuname>_m2O
ARLOCKarlock_<tbuname>_s1Iarlock_<tbuname>_m1O
ARCACHEarcache_<tbuname>_s4Iarcache_<tbuname>_m4O
ARPROTarprot_<tbuname>_s3Iarprot_<tbuname>_m3O
ARVALIDarvalid_<tbuname>_s1Iarvalid_<tbuname>_m1O
ARREGIONarregion_<tbuname>_s4Iarregion_<tbuname>_m4O
ARQOSarqos_<tbuname>_s4Iarqos_<tbuname>_m4O
ARSNOOParsnoop_<tbuname>_s4Iarsnoop_<tbuname>_m4O
ARBARarbar_<tbuname>_s2Iarbar_<tbuname>_m2O
ARDOMAINardomain_<tbuname>_s2Iardomain_<tbuname>_m2O
ARUSERaruser_<tbuname>_s(IAUW-2)[c]Iaruser_<tbuname>_m(IAUW+2)[c]O
ARREADYarready_<tbuname>_s1Oarready_<tbuname>_m1I

[a] The slave ID width, SIW, that is the same as the configured AXI ID signal width parameter. See Configurable options for more information.

[b] The master ID width, MIW, is the calculated output ID width. See Output ID width for more information.

[c] The INPUT_AUSER_WIDTH, IAUW. See ACE-Lite signals for more information.


Table A.9 shows the ACE-Lite read address channel signals for the TCU.

Table A.10. TCU read address channel signals

ACE-LiteTCU slave portWidthI/OTCU master portWidthI/O
ARIDarid_prog(AXIPID+1)[a]Iarid_ptwMIW[b]O
ARADDRaraddr_prog32Iaraddr_ptw48O
ARLENarlen_prog8Iarlen_ptw8O
ARSIZEarsize_prog3Iarsize_ptw3O
ARBURSTarburst_prog2Iarburst_ptw2O
ARLOCKarlock_prog1Iarlock_ptw1O
ARCACHEarcache_prog4Iarcache_ptw4O
ARPROTarprot_prog3Iarprot_ptw3O
ARVALIDarvalid_prog1Iarvalid_ptw1O
ARREGIONarregion_prog4Iarregion_ptw4O
ARQOSarqos_prog4Iarqos_ptw4O
ARSNOOP---arsnoop_ptw4O
ARBAR---arbar_ptw2O
ARDOMAIN---ardomain_ptw2O
ARUSER---aruser_ptw6[c]O
ARREADYarready_prog1Oarready_ptw1I

[a] The AXI programming interface ID signal width, AXIPID, is the AXI programming interface ID signal width parameter. See Configurable options for more information.

[b] The master ID width, MIW, is the calculated output ID width. See Output ID width for more information.

[c] The bit assignments are as follows:

[5:2]

Inner cache attributes for the PTW.

[1]

Outer transient attribute for the PTW.

[0]

Inner transient attribute for the PTW.


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