A.4.4. Tie-off signals

Table A.20 shows the tie-off signals.

Table A.20. Tie-off signals

SignalI/OWidthDescription
cfg_cttwI1

Indicates whether the system supports coherent page table walks.

This information is also shown in the SMMU_IDR0. The signal value does not have any impact on the way the MMU-500 generates accesses. Instead, the signal value is generated by the system integrator and it is used to check the coherency of the system to which the TCU is connected.

You can specify one of the following options:

0b0

The MMU-500 is connected to an interconnect that supports cache coherency for the PTWs.

0b1

The system does not support coherent PTWs.

dftclkenableI1

When this signal is HIGH, the MMU-500 bypasses architectural clock gates. This signal is used in the DFT test mode. You can specify one of the following values:

0b0

Functional mode.

0b1

Bypass architectural clock gates in the DFT test mode.

integ_sec_overrideI1

When this signal is set, Non-secure accesses can access the integration registers. See Integration registers

Note

When this signal is HIGH, you must tie the spniden input signal LOW.

sysbardisable_<tbuname>I1

Specifies whether the MMU-500 can generate barriers or not. You can specify one of the following options:

0b0

The MMU-500 generates barriers and transmits the barriers that it receives.

0b1

The MMU-500 does not generate barriers. However, it must transmits the barriers it receives from the master connected to it.

dftmcphold I1This signal must be tied HIGH when TCU half clock configuration is selected to enable scan testing.

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