| Copyright © 2013, 2014 ARM. All rights reserved. | ARM DDI 0517C |
| Non-Confidential | ID031814 |
 PDF version | |
| Home > Functional Description > Cache structures of the MMU-500 > IPA to PA cache |
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The MMU-500 implements an IPA to PA cache for stage 1 followed by stage 2 translations.
The IPA to PA cache is a single four-way set associative cache that you can enable or disable depending on the context. The IPA to PA cache shares RAMs with the PTW cache. See Page table walk cache.
| Copyright © 2013, 2014 ARM. All rights reserved. | ARM DDI 0517C |
| Non-Confidential | ID031814 |
| PDF version | |
| Home > Functional Description > Cache structures of the MMU-500 > IPA to PA cache |