3.8.3. Integration Test Output Global register

The SMMU_ITOP_GLBL register characteristics are:

Purpose

Enables the MMU-500 to set the status of the signals as Table 3.21 shows.

Configuration

Available in all MMU-500 configurations.

Attributes

Figure 3.9 shows the bit assignments.

Figure 3.9. SMMU_ITOP_GLBL register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 3.21 shows the bit assignments.

Table 3.21. SMMU_ITOP_GLBL register bit assignments

BitsName Reset valueDescription
[31:23]Reserved-Reserved.
[22:16]TCU_RAM_DATA-

This RW bit field has a variable width in the range of 1-log2(Number of contexts), for MTLB or IPA RAMs.

This bit field is enabled only for TCU RAMs that is when the SMMU_ITCTRL.RAM_MODE bit is set to 0b1 and the SMMU_ITCTRL.MODULE bit is set to 0b0.

The SMMU_ITCTRL.RAM_DATA bit indicates read or write access information and the access direction.

The bit field corresponds to the most significant bits of the RAM RW data. The MSB bits for the MTLB or IPA RAMs can be one of the following:

[97:91]

For only stage 2 translations.

[129:123]

For stage 1, stage 2, and stage 1 followed by stage 2 translations.

[15:10]Reserved-Reserved.
[9]GLBLSFI-

Global Secure fault interrupt. The value of this bit is equal to the value of the gbl_flt_irpt_s signal.

This bit can have one of the following values:

0b0

Disable global Secure fault interrupt.

0b1

Enable global Secure fault interrupt.

[8:2]Reserved-Reserved.
[1]GLBLNSFI-

Global Non-secure fault interrupt. The value of this bit is equal to the value of the glbl_flt_irpt_ns signal.

This bit can have one of the following values:

0b0

Disable global Non-secure fault interrupt.

0b1

Enable global Non-secure fault interrupt.

[0]Reserved-Reserved.

Copyright © 2013, 2014, 2016 ARM. All rights reserved.ARM DDI 0517F
Non-ConfidentialID041216