3.7.1. Auxiliary Control registers

The SMMU_CBn_ACTLR characteristics are:

Purpose

Enable context caching in the macro TLB or prefetch buffer.

Configuration

Available in all MMU-500 configurations.

Usage constraints

You must modify this register only during the MMU-500 initialization, otherwise the register modification invalidates all TCU caches.

Note

You can modify this register only when the ACR.CACHE_LOCK bit is 0.

Attributes

Figure 3.6 shows the bit assignments.

Figure 3.6. SMMU_CBn_ACTLR registers bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 3.18 shows the bit assignments.

Table 3.18. SMMU_CBn_ACTLR registers bit assignments

BitsName Reset valueDescription
[31:2]Reserved-Reserved.
[1]CPRE0b1Enable context caching in the prefetch buffer.
[0]CMTLB0b1Enable context caching in the macro TLB.

Copyright © 2013, 2014, 2016 ARM. All rights reserved.ARM DDI 0517F
Non-ConfidentialID041216