3.8.5. Integration Test Output Context Interrupt registers

The SMMU_ITOP_CXTnTOm_RAMx registers characteristics are:

Purpose

Enable the context performance interrupts. The MMU-500 provides the following context performance registers that you can use to select contexts 0-31, 32-63, 64-95, or 96-127:

SMMU_ITOP_CXT0TO31_RAM0

Register for contexts 0-31.

SMMU_ITOP_CXT32TO63_RAM1

Register for contexts 32-63.

SMMU_ITOP_CXT64TO95_RAM2

Register for contexts 64-95.

SMMU_ITOP_CXT96TO127_RAM3

Register for contexts 96-127.

Configuration

Available in all MMU-500 configurations.

Usage constraints

The value of the SMMU_ITCTRL.RAM_MODE bit defines the behavior of this register, as follows:

  • If the bit is set to 0b0, the register specifies the context interrupt to enable.

  • If the bit is set to 0b1, the register specifies the RAM information.

Attributes

Figure 3.13 shows the bit assignments when the SMMU_ITCTRL.RAM_MODE bit is set to 0b0.

Figure 3.13. SMMU_ITOP_CXTnTOm_RAMx registers bit assignments-SMMU_ITCTRL.RAM_MODE0

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Table 3.25 shows the bit assignments when the SMMU_ITCTRL.RAM_MODE bit is set to 0b0.

Table 3.25. SMMU_ITOP_CXTnTOm_RAMx registers bit assignments-SMMU_ITCTRL.RAM_MODE0

BitsName Reset valueDescription
[31:0]CONINT-

The context interrupt to be enabled or disabled. This bit is WO.

Bitn

Represents the performance interrupt for context n. This bit can have one of the following values:

0b1

Enable the performance interrupt for context n.

0b0

Disable the performance interrupt for context n.


Figure 3.13 shows the bit assignments when the SMMU_ITCTRL.RAM_MODE bit is set to 0b1.

Figure 3.14. SMMU_ITOP_CXTnTOm_RAMx registers bit assignments-SMMU_ITCTRL.RAM_MODE1

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Table 3.25 shows the bit assignments when the SMMU_ITCTRL.RAM_MODE bit is set to 0b1.

Table 3.26. SMMU_ITOP_CXTnTOm_RAMx registers bit assignments-SMMU_ITCTRL.RAM_MODE1

BitsName Reset valueDescription
[31:0]RAM_DATA-

The RAM data.

The SMMU_ITCTRL.RAM_DATA bit indicates read or write access information and the access direction.


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