3.8.7. Parity Error Checker Register

The SMMU_PER characteristics include:

Purpose

Checks for parity errors in TCU and TBU RAMs.

Configuration

Available in all MMU-500 configurations.

Attributes

Figure 3.16 shows the bit assignments.

Figure 3.16. SMMU_PER register bit assignments

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Table 3.28 shows the bit assignments.

Table 3.28. SMMU_PER register bit assignments

BitsName Reset valueDescription
[31:16]Reserved-Reserved.
[15:8]PER_TCU0x00Parity errors found in TCU RAMs. This bit field saturates after reaching the maximum value.
[7:0]PER_TBU0x00Parity errors found in TBU RAMs. This bit field saturates after reaching the maximum value.

Note

The TBU micro TLB, the TCU macro TLB and the walk cache RAMs support single bit error detection and invalidation on error detection. The TCU MFIFO RAM supports the single bit error detection and correction.

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