16-deep TBU queue support.

32-deep write buffer support.

Support for half-clock configuration. The TCU core runs at half the speed of the I/O clock, permitting the synchronous interfaces to run at a higher clock speed. The clock division is handled internally by the TCU.

Ability to configure the StreamID width as 15 bits.

Support for up to 256 outstanding transactions for read and write channels on the TBU master interface.

Support for normalization.

No technical updates.

Change to behavior to prevent cases where a Sync complete transaction fails to generate when a stalled transaction exists.

Change to behavior to prevent starvation of entries in the PTW queue when the queue is full.