3.5.2. Debug registers

Purpose

Use the debug AXI4 programming interface for the following information:

  • The data stored in the TLB tag. This data is used for transaction matching.

  • The physical address and its attributes. These are used for data transactions.

The MMU-500 supports TLB visibility by providing read pointer registers and read data registers to read the values.

On a read access to a TLB data register, the MMU-500 performs the following:

  1. Initializes, that is sets to zero, the read pointer register.

  2. Increments the read pointer register by one word, that is, four bytes.

  3. Reads the TLB data from the read pointer registers.

  4. Returns the TLB data on the AXI4 programming interface.

The read pointer register is writable, but the read data register is read-only. The two lower bits of the read pointer registers are RAZ/WI. This ensures that the addresses for a debug TLB fetch are always word aligned.

If the read pointer registers are written with address values that are out-of-bounds of the TLB, the MMU-500 returns zero on the AXI4 programming interface.

See Table 3.3.

The following registers define the TLB access mechanism:

SMMU_GR0_BASE+0x80

TBU-TLB read pointer register - only Secure domain access.

SMMU_GR0_BASE+0x84

TBU-TLB read data register - only Secure domain access. This 32-bit register contains the part of the TLB pointed to by the read pointer register.

SMMU_GR0_BASE+0x88

TCU-TLB read pointer register - only Secure domain access.

SMMU_GR0_BASE+0x8C

TCU-TLB read data register - only Secure domain access. This is a 32-bit register that contains the part of the TLB pointed by the read pointer register.

You can read specific TLB entries by programming the read pointer registers. On an access to the read data register, the MMU-500 returns the TLB entry specified by the read pointer registers and increments the read pointer register. For the next access to the read data register, the MMU-500 reads the read data registers again and returns the next TLB entry.

Note

ARM recommends that you perform a TLB read access when there are no pending transactions. If the TLB read occurs concurrently with transactions, the TLB read can return data before or after the data is updated.

The MMU-500 contains the following debug registers:

Configuration

Available in all MMU-500 configurations.

Usage constraints

Only Secure access is possible.

Attributes

TBU-TLB Debug Read Pointer register

Bits[31:16] are always 0 unless specified by an AXI4 access.

Figure 3.4 shows the bit assignments.

Figure 3.4. SMMU_DBGRPTRTBU register bit assignments

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Table 3.9 shows the bit assignments.

Table 3.9. SMMU_DBGRPTRTBU register bit assignments

BitsNameReset valueDescription
[31:24]TBU ID0x00TBU identifier. Specifies the TBU from which to read the data. The range of values depends on the number of TBUs configured.
[23:16]Reserved-Reserved.
[15:4]TLB Pointer0x000The pointer to the specified TLB entry.
[3:0]TLB Entry Pointer0x0Words within the TLB entry.

TCU-TLB Debug Read Pointer register

Bits[31:16] are always 0 unless specified by an AXI4 access.

Figure 3.5 shows the bit assignments.

Figure 3.5. SMMU_DBGRPTRTCU register bit assignments

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Table 3.10 shows the bit assignments.

Table 3.10. SMMU_DBGRPTRTCU register bit assignments

BitsNameReset valueDescription
[31:28]Reserved-Reserved.
[27:26]DATASRC-

Specifies the source from which to read the data. This bit field can have one of the following values:

0b00

Macro TLB.

0b01

Prefetch buffer.

0b10

IPA to PA translation cache.

0b11

Walk cache.

[25:24]WAY_RAM0b00

The way in which to connect the four-way set associative cache. This bit field can have one of the following values:

0b00

RAM 1.

0b01

RAM 2.

0b10

RAM 3.

0b11

RAM 4.

[23:16]Reserved-Reserved.
[15:4]TLB Pointer 0x000The pointer to the specified TLB entry.
[3:0]TLB Entry Pointer0x0Words within the TLB entry.

Debug Read Data registers

Table 3.11 shows the Debug Read Data register data format, word 0.

Note

If a parity error occurs because of a soft error in a TBU TLB RAM, and if the entry is invalid, the debug read data can be corrupted and contain an incorrect value.

Table 3.11. Debug read data register data format, word 0

BitsWidthDescription
[31:4]28The virtual address to use for address lookup.
[3:2]2

TLB_WORD_INFO. This bit specifies whether the TLB word information is valid.

This bit can have one of the following values:

0b0

Valid.

0b1

Invalid.

[1]1

TLB_POINTER_VALID. This bit specifies whether the TLB pointer is valid. This bit can have one of the following values:

0b0

Valid.

0b1

Invalid.

[0]1

TLB_ENTRY_VALID. This bit field specifies whether the TLB entry is valid. This bit field can have one of the following values:

0b00

A word that is not the first or the last of the TLB entry.

0b01

First word of the TLB entry.

0b10

Last word of the TLB entry.

0b11

First word of the TLB.


Table 3.12 shows the Debug Read Data register data format, word 1. For more information, see the ARM® System Memory Management Unit Architecture Specification.

Table 3.12. Debug read data register data format, word 1

BitsWidthDescription
[31:16]16ASID, Address space identifier.
[15]1NSSTATE, Non-secure state.
[14:13]2

The entry type. This bit field can have one of the following values:

0b00

The translation is enabled.

0b01

The translation is disabled.

0b10

The stage to context register bypass information as programmed in the SMMU_S2CRn register.

0b11

The SMMU_CR0.USFCFG bit is set.

[12:4]9The virtual address to use for address lookup.
[3:2]2

TLB_ENTRY_VALID. See Table 3.11.

[1]1

TLB_POINTER_VALID. See Table 3.11.

[0]1

TLB_WORD_INFO. See Table 3.11.


Table 3.13 shows the Debug Read Data register data format, word 2.

Table 3.13. Debug read data register data format, word 2

BitsWidthDescription
[31:4]28Physical address [39:12] bits.
[3:2]2

TLB_ENTRY_VALID. See Table 3.11.

[1]1

TLB_POINTER_VALID. See Table 3.11.

[0]1

TLB_WORD_INFO. See Table 3.11.


Table 3.14 shows the Debug Read Data register data format, word 3.

Table 3.14. Debug read data register data format, word 3

BitsWidthDescription
[31]1

UCI, User Cache Maintenance Operation Enable. See Additional reading for more information on the usage of this bit.

[30]1

MMU-500 Enable. This is the global enable bit for the translation context bank. This bit can have one of the following values:

0b0

The MMU-500 behavior for the translation context bank is disabled.

0b1

The MMU-500 behavior for the translation context bank is enabled.

[29]1

S2 RW64. See the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile.

[28]1

S1 RW64. See the ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile.

[27]1

S1 EAE. See the following documents for more information on LPAE addresses:

  • ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition.

  • ARM® Architecture Reference Manual, ARMv8, for ARMv8-A architecture profile.

[26:20]7Translation Context Index.
[19]1Reserved.
[18:16]3

Stage 2 Page Size. This bit field can have one of the following values:

0b000

4KB.

0b001

64KB.

0b010

Reserved.

0b011

2MB.

0b100

Reserved.

0b101

Reserved.

0b110

512MB.

0b111

1GB.

[15:13]3

Stage 1 Page Size. This bit field can have one of the following values:

0b000

4KB.

0b001

64KB.

0b010

1MB.

0b011

2MB.

0b100

16MB.

0b101

Reserved.

0b110

512MB.

0b111

1GB.

[12]1Not global. Determines how the translation is marked in the TLB. See the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition.
[11:4]8Physical Address [47:40] bits.
[3:2]2

TLB_ENTRY_VALID. See Table 3.11.

[1]1

TLB_POINTER_VALID. See Table 3.11.

[0]1

TLB_WORD_INFO. See Table 3.11.


Table 3.15 shows the Debug Read Data register data format, word 4. For more information, see the ARM® System Memory Management Unit Architecture Specification.

Table 3.15. Debug read data register data format, word 4

BitsWidthDescription
[31:30]2NSCFG, Non-secure configuration.
[29:27]3SHCFG, shareability configuration.
[26:25]2Inner RACFG, read allocate configuration.
[24:23]2Outer RACFG, read allocate configuration.
[22:21]2Inner WACFG, write allocate configuration.
[20:19]2Outer WACFG, write allocate configuration.
[18]1PXN, privilege execute never.
[17]1Stage 2 XN, execute never.
[16]1Stage 1 XN, execute never.
[15:13]3Reserved.
[12:11]2HAP, stage 2 access permissions bits.
[10:8]3AP, access permissions bits.
[7:6]2PRIVCFG, privilege configuration.
[5:4]2INSTCFG, instruction configuration.
[3:2]2

TLB_ENTRY_VALID. See Table 3.11.

[1]1

TLB_POINTER_VALID. See Table 3.11.

[0]1

TLB_WORD_INFO. See Table 3.11.


Table 3.16 shows the Debug Read Data register data format, word 5. For more information, see the ARM® System Memory Management Unit Architecture Specification.

Table 3.16. Debug read data register data format, word 5

BitsWidthDescription
[31:26]6Reserved.
[25:20]6Stream ID mask [15:10] when StreamID is configured as 15 bits.
[19:14]6Stream ID [15:10] when StreamID is configured as 15 bits.
[13]1The parity bit.
[12:11]2Inner TRANSIENTCFG, transient configuration, controls the transient allocation hint.
[10:9]2Outer TRANSIENTCFG, transient configuration, controls the transient allocation hint.
[8:4]5

Memory Attribute. The memory attributes can be overlaid if SMMU_CBn_SCTLR.M is set to 0b0.

[3:2]2

TLB_ENTRY_VALID. See Table 3.11.

[1]1

TLB_POINTER_VALID. See Table 3.11.

[0]1

TLB_WORD_INFO. See Table 3.11.


Table 3.17 shows the Debug Read Data register data format, word 6.

Table 3.17. Debug read data register data format, word 6

BitsWidthDescription
[31:24]8Reserved.
[23:14]10The StreamID mask.
[13:4]10The StreamID.
[3:2]2

TLB_ENTRY_VALID. See Table 3.11.

[1]1

TLB_POINTER_VALID. See Table 3.11.

[0]1

TLB_WORD_INFO. See Table 3.11.


Performance monitoring

The MMU-500 supports performance monitoring as explained in the ARM® System Memory Management Unit Architecture Specification. One counter group is provided for every TBU that can be used as a global group, as part of a context, or as a stream. The MMU-500 supports four event counters as a global group, and all event classes specified in the ARM® System Memory Management Unit Architecture Specification:

  • Each TBU contains all performance counters.

  • When performance registers are programmed, the TCU sends the setup information for the counter messages to the TBUs.

  • On counter overflows, the TBUs pass the information to the TCU, and the TCU raises an interrupt.

  • The TCU can also send a request to the TBUs for the current state of the counters.

    Note

    When the TBU is powered down, the counter data is invalid.

  • If the counter value is preset, the TCU updates the TBUs.

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