A.1. Clock and reset signals

This section describes the clock and reset signals of the MMU-500.

Table A.1 shows the clock and reset signals of the TCU.

Table A.1. TCU clock and reset signals

SignalWidthI/ODescription
cclk1IClock for the TCU.
cresetn1IReset for the TCU.

Table A.2 shows the clock and reset signals of the TBU.

Table A.2. TBU clock and reset signals

SignalWidthI/ODescription
<tbuname>_bclkn1I

TBUn clock, where n is a value in the range 0-31.

If configured to have a separate PTW AXI port, the clock supplied to TBU0 also clocks the multiplexer between TBU0 and the TCU.

<tbuname>_bresetn1ITBUn reset, where n is a value in the range 0-31.

Note

When PTW has a separate AXI port is set to zero, then these two clocks and resets must be the same.

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