A.2.3. Write response channel signals

Table A.7 shows the ACE-Lite write response channel signals for the TBU.

Table A.7. TBU write response channel signals

ACE-LiteTBU slave portWidthI/OTBU master portWidthI/O
BIDbid_<tbuname>_sSIW[a]Obid_<tbuname>_mMIW[b]I
BRESPbresp_<tbuname>_s2Obresp_<tbuname>_m2I
BVALIDbvalid_<tbuname>_s1Obvalid_<tbuname>_m1I
BUSERbuser_<tbuname>_sBUSER[c]Obuser_<tbuname>_mBUSERI
BREADYbready_<tbuname>_s1Ibready_<tbuname>_m1O

[a] The slave ID width, SIW, that is the same as the configured AXI ID signal width. See Configurable options for more information.

[b] The master ID width, MIW, is the calculated output ID width. See Output ID width for more information.

[c] The width of the buser signal, specified by the Width of the AXI slave interface BUSER signals parameter. See Configurable options for more information.


Table A.7 shows the ACE-Lite write response channel signals for the TCU.

Table A.8. TCU write response channel signals

ACE-LiteTCU slave portWidthI/OTCU master port[a]WidthI/O
BIDbid_prog(AXIPID+1)[b]Obid_ptwMIW[c]I
BRESPbresp_prog2Obresp_ptw2I
BVALIDbvalid_prog1Obvalid_ptw1I
BUSER---buser_ptwBUSERI
BREADYbready_prog1Ibready_ptw1O

[a] For PTW, the write response channel signals are unused.

[b] The AXI programming interface ID signal width, AXIPID, is the AXI programming interface ID signal width parameter. See Configurable options for more information.

[c] The master ID width, MIW, is the calculated output ID width. See Output ID width for more information.


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