A.2.1. Write address channel signals

Table A.3 shows the ACE-Lite write address channel signals for the TBU.

Note

The *_prog signals follow the AXI4 protocol, and the TBU signals follow the ACE-Lite protocol.

Table A.3. TBU write address channel signals

ACE-LiteTBU slave portWidthI/OTBU master portWidthI/O
AWIDawid_<tbuname>_s[a]SIWIawid_<tbuname>_m[b]MIWO
AWADDRawaddr_<tbuname>_s49Iawaddr_<tbuname>_m48O
AWLENawlen_<tbuname>_s8Iawlen_<tbuname>_m8O
AWSIZEawsize_<tbuname>_s3Iawsize_<tbuname>_m3O
AWBURSTawburst_<tbuname>_s2Iawburst_<tbuname>_m2O
AWLOCKawlock_<tbuname>_s1Iawlock_<tbuname>_m1O
AWCACHEawcache_<tbuname>_s4Iawcache_<tbuname>_m4O
AWPROTawprot_<tbuname>_s3Iawprot_<tbuname>_m3O
AWVALIDawvalid_<tbuname>_s1Iawvalid_<tbuname>_m1O
AWREGIONawregion_<tbuname>_s4Iawregion_<tbuname>_m4O
AWQOSawqos_<tbuname>_s4Iawqos_<tbuname>_m4O
AWSNOOPawsnoop_<tbuname>_s3Iawsnoop_<tbuname>_m3O
AWBARawbar_<tbuname>_s2Iawbar_<tbuname>_m2O
AWDOMAINawdomain_<tbuname>_s2Iawdomain_<tbuname>_m2O
AWUSERawuser_<tbuname>_s(IAUW-2)[c]Iawuser_<tbuname>_m(IAUW+2)[c]O
AWREADYawready_<tbuname>_s1Oawready_<tbuname>_m1I

[a] The slave ID width, SIW, that is the same as the configured AXI ID signal width. See Configurable options for more information.

[b] The master ID width, MIW, is the calculated output ID width. See Output ID width for more information.

[c] The INPUT_AUSER_WIDTH, IAUW. See ACE-Lite signals.


Table A.4 shows the ACE-Lite write address channel signals for the TCU.

Note

AW, W, and B channels of the PTW interface are not used.

Table A.4. TCU write address channel signals

ACE-LiteTCU slave portWidthI/OTCU master port[a]WidthI/O
AWIDawid_prog(AXIPID+1)[b]Iawid_ptwMIW[c]O
AWADDRawaddr_prog32Iawaddr_ptw48O
AWLENawlen_prog8Iawlen_ptw8O
AWSIZEawsize_prog3Iawsize_ptw3O
AWBURSTawburst_prog2Iawburst_ptw2O
AWLOCKawlock_prog1Iawlock_ptw1O
AWCACHEawcache_prog4Iawcache_ptw4O
AWPROTawprot_prog3Iawprot_ptw3O
AWVALIDawvalid_prog1Iawvalid_ptw1O
AWREGIONawregion_prog4Iawregion_ptw4O
AWQOSawqos_prog4I---
AWSNOOP---awsnoop_ptw3O
AWBAR---awbar_ptw2O
AWDOMAIN---awdomain_ptw2O
AWUSER---awuser_ptw6O
AWREADYawready_prog1Oawready_ptw1I

[a] For PTW, the write address channel signals are unused.

[b] The AXI programming interface ID signal width, AXIPID, is the AXI programming interface ID signal width. See Configurable options for more information.

[c] The master ID width, MIW, is the calculated output ID width. See Output ID width for more information.


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