ARM CoreLink MMU-500 System Memory Management Unit Technical Reference Manual: A.2.1. Write address channel signals

Table A.3 shows the ACE-Lite write address channel signals for the TBU.

The *_prog signals follow the AXI4 protocol, and the TBU signals follow the ACE-Lite protocol.

Table A.3. TBU write address channel signals

ACE-Lite	TBU slave port	Width	I/O	TBU master port	Width	I/O
AWID	awid_<tbuname>_s^[a]	SIW	I	awid_<tbuname>_m^[b]	MIW	O
AWADDR	awaddr_<tbuname>_s	49	I	awaddr_<tbuname>_m	48	O
AWLEN	awlen_<tbuname>_s	8	I	awlen_<tbuname>_m	8	O
AWSIZE	awsize_<tbuname>_s	3	I	awsize_<tbuname>_m	3	O
AWBURST	awburst_<tbuname>_s	2	I	awburst_<tbuname>_m	2	O
AWLOCK	awlock_<tbuname>_s	1	I	awlock_<tbuname>_m	1	O
AWCACHE	awcache_<tbuname>_s	4	I	awcache_<tbuname>_m	4	O
AWPROT	awprot_<tbuname>_s	3	I	awprot_<tbuname>_m	3	O
AWVALID	awvalid_<tbuname>_s	1	I	awvalid_<tbuname>_m	1	O
AWREGION	awregion_<tbuname>_s	4	I	awregion_<tbuname>_m	4	O
AWQOS	awqos_<tbuname>_s	4	I	awqos_<tbuname>_m	4	O
AWSNOOP	awsnoop_<tbuname>_s	3	I	awsnoop_<tbuname>_m	3	O
AWBAR	awbar_<tbuname>_s	2	I	awbar_<tbuname>_m	2	O
AWDOMAIN	awdomain_<tbuname>_s	2	I	awdomain_<tbuname>_m	2	O
AWUSER	awuser_<tbuname>_s	(IAUW-2)^[c]	I	awuser_<tbuname>_m	(IAUW+2)^[c]	O
AWREADY	awready_<tbuname>_s	1	O	awready_<tbuname>_m	1	I
^[a]The slave ID width, SIW, that is the same as the configured `AXI ID signal width`. See Configurable options for more information. ^[b]The master ID width, MIW, is the calculated output ID width. See Output ID width for more information. ^[c]The INPUT_AUSER_WIDTH, IAUW. See ACE-Lite signals.

Table A.4 shows the ACE-Lite write address channel signals for the TCU.

AW, W, and B channels of the PTW interface are not used.

Table A.4. TCU write address channel signals

ACE-Lite	TCU slave port	Width	I/O	TCU master port^[a]	Width	I/O
AWID	awid_prog	(AXIPID+1)^[b]	I	awid_ptw	MIW^[c]	O
AWADDR	awaddr_prog	32	I	awaddr_ptw	48	O
AWLEN	awlen_prog	8	I	awlen_ptw	8	O
AWSIZE	awsize_prog	3	I	awsize_ptw	3	O
AWBURST	awburst_prog	2	I	awburst_ptw	2	O
AWLOCK	awlock_prog	1	I	awlock_ptw	1	O
AWCACHE	awcache_prog	4	I	awcache_ptw	4	O
AWPROT	awprot_prog	3	I	awprot_ptw	3	O
AWVALID	awvalid_prog	1	I	awvalid_ptw	1	O
AWREGION	awregion_prog	4	I	awregion_ptw	4	O
AWQOS	awqos_prog	4	I	-	-	-
AWSNOOP	-	-	-	awsnoop_ptw	3	O
AWBAR	-	-	-	awbar_ptw	2	O
AWDOMAIN	-	-	-	awdomain_ptw	2	O
AWUSER	-	-	-	awuser_ptw	6	O
AWREADY	awready_prog	1	O	awready_ptw	1	I
^[a]For PTW, the write address channel signals are unused. ^[b]The AXI programming interface ID signal width, AXIPID, is the `AXI programming interface ID signal width`. See Configurable options for more information. ^[c]The master ID width, MIW, is the calculated output ID width. See Output ID width for more information.

Copyright © 2013, 2014, 2016 ARM. All rights reserved.	ARM DDI 0517F
Non-Confidential	ID041216
PDF version