2.4.2. Macro TLB

The macro TLB caches PTW results in the TCU. You can configure the depth of the macro TLB based on your requirements.

Figure 2.8 shows the TCU cache structure that consists of macro TLBs, prefetch buffers, IPA2PA cache, and PTW caches.

Figure 2.8. TCU cache

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


See Additional reading for more information on the TCU configurability.

Copyright © 2013, 2014, 2016 ARM. All rights reserved.ARM DDI 0517F
Non-ConfidentialID041216