CoreLink™ MMU-401 System Memory Management Unit Technical Reference Manual

Revision: r0p0


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the MMU-401
1.2. Features of the MMU-401
1.3. Implementation options for synthesis
1.4. Product revisions
2. Functional Description
2.1. Interfaces
2.1.1. Programming interface
2.1.2. AXI3, AXI4, or ACE-Lite interface
2.1.3. Low-power interface and clock gating
2.2. Stream ID
2.3. Security determination
2.4. Hit-Under-Miss
2.5. Fault handling
2.6. Dynamic programming
3. Programmers Model
3.1. About the programmers model
3.2. The MMU-401 address map
3.3. Register summary
3.3.1. Global space 0 registers summary
3.3.2. Global space 1 registers summary
3.3.3. Integration register summary
3.3.4. Performance monitoring registers summary
3.3.5. Security state determination address space summary
3.3.6. Peripheral and Component identification registers summary
3.3.7. Translation context-bank registers summary
3.4. Global register space 0
3.4.1. Secure configuration register 0
3.4.2. Auxiliary configuration registers
3.4.3. Identification registers
3.4.4. Debug registers
3.4.5. Secure alias to Non-secure configuration register 0
3.4.6. Secure Alias to Non-secure auxiliary configuration register
3.4.7. Stream match registers
3.4.8. Stream to context registers
3.5. Global register space 1
3.5.1. Context-bank attribute registers
3.5.2. Context-bank fault restricted syndrome registers A
3.6. Integration registers
3.6.1. Integration enable register
3.6.2. Integration test input register
3.6.3. Integration test output register
3.7. Performance monitoring registers
3.7.1. Performance monitor counter group configuration registers
3.7.2. Performance monitor counter group stream match registers
3.7.3. Performance monitor configuration register
3.7.4. Performance monitor control register
3.7.5. Performance monitor authentication status register
3.7.6. Performance monitor device type register
3.8. Security state determination address space
3.9. Peripheral and component identification registers
3.9.1. Component identification registers
3.9.2. Peripheral identification registers
3.10. Translation context-bank registers
3.10.1. System control register
3.10.2. Translation table base control register
A. Signal Descriptions
A.1. Clock and resets
A.2. AXI3 signals
A.2.1. Write address channel signals
A.2.2. Write data channel signals
A.2.3. Write response channel signals
A.2.4. Read address channel signals
A.2.5. Read data channel signals
A.3. AXI4 signals
A.3.1. Write address channel signals
A.3.2. Write data channel signals
A.3.3. Write response channel signals
A.3.4. Read address channel signals
A.3.5. Read data channel signals
A.4. ACE-Lite signals
A.4.1. Write address channel signals
A.4.2. Write data channel signals
A.4.3. Write response channel signals
A.4.4. Read address channel signals
A.4.5. Read data channel signals
A.4.6. Snoop channel signals
A.5. APB signals
A.5.1. APB4 signals
A.5.2. APB3 signals
A.6. LPI signals
A.7. Miscellaneous signals
A.7.1. Sideband signals
A.7.2. Interrupt signals
A.7.3. MBIST signals
A.7.4. Authentication interface signal
A.7.5. Tie-off signals
A.7.6. Performance event signals
B. Revisions

List of Figures

1. Key to timing diagram conventions
1.1. MMU-401 in system context
2.1. MMU-401 block diagram
3.1. MMU-401 address map
3.2. Secure configuration register 0 bit assignments
3.3. Auxiliary configuration registers bit assignments
3.4. Identification register 0 bit assignments
3.5. Identification register 1 bit assignments
3.6. Identification register 2 bit assignments
3.7. Identification register 7 bit assignments
3.8. Debug read pointer register bit assignments
3.9. Stream match registers bit assignments
3.10. Stage 2 context, TYPE==00 bit assignments
3.11. Context-bank restricted syndrome register bit assignments
3.12. Integration enable register bit assignments
3.13. Integration test input register bit assignments
3.14. Integration test output register bit assignments
3.15. Performance monitor counter group configuration registers bit assignments
3.16. Performance monitor counter group stream match registers bit assignments
3.17. Performance Monitor Configuration Register bit assignments
3.18. Performance monitor control register bit assignments
3.19. Performance monitor authentication status register assignments
3.20. Performance monitor device type register bit assignments
3.21. Component identification register bit assignments
3.22. Peripheral identification register 0 bit assignments
3.23. Peripheral identification register 1 bit assignments
3.24. Peripheral identification register 2 bit assignments
3.25. Peripheral identification register 3 bit assignments
3.26. Peripheral identification register 4 bit assignments
3.27. Peripheral identification registers 5-7 bit assignments
3.28. System control register bit assignment
3.29. Translation table base control register bit assignments

List of Tables

1. Typographical conventions
1.1. Implementation options for synthesis
3.1. Global space 0 registers summary
3.2. Global space 1 register summary
3.3. Integration registers summary
3.4. Performance monitoring registers summary
3.5. The MMU-401 security state determination address space summary
3.6. Peripheral and component identification summary
3.7. Translation context-bank address map summary
3.8. Secure configuration register 0 bit assignments
3.9. Auxiliary configuration registers bit assignments
3.10. Identification register 0 bit assignments
3.11. Identification register 1 bit assignments
3.12. Identification register 2 bit assignments
3.13. Identification register 7 bit assignments
3.14. Debug read pointer register bit assignments
3.15. Debug read data register data format, word 1
3.16. Debug read data register data format, word 2
3.17. Debug read data register data format, word 3
3.18. Debug read data register data format, word 4
3.19. Debug read data register data format, word 5
3.20. Stream match registers bit assignments
3.21. Context-bank attribute register
3.22. Stage 2 context, TYPE==00 bit assignments
3.23. Context-bank restricted syndrome register bit assignments
3.24. Integration enable register bit assignments
3.25. Integration test input register bit assignments
3.26. Integration test output register bit assignments
3.27. Performance monitor counter group configuration register bit assignments
3.28. Performance monitor counter group stream match registers bit assignments
3.29. Performance Monitor Configuration Register bit assignments
3.30. Performance monitor control register bit assignments
3.31. Action on writes to the count enable bit
3.32. Performance monitor authentication status register bit assignments
3.33. Performance monitor device type register bit assignments
3.34. Security state determination address space
3.35. Component identification register bit assignments
3.36. Peripheral identification register 0 bit assignments
3.37. peripheral identification register 1 bit assignments
3.38. Peripheral identification register 2 bit assignments
3.39. Peripheral identification register 3 bit assignments
3.40. Peripheral identification register 4 bit assignments
3.41. Peripheral identification registers 5-7 bit assignments
3.42. System control register bit assignment
3.43. MemAttr bit values
3.44. Secondary MemAttr bit values
3.45. Translation table base control register bit assignments
A.1. PTW block� clock and reset signals
A.2. �TLB block clock and reset signals
A.3. Write address channel signals
A.4. Write data channel signals for the slave port of the TLB block
A.5. Write data channel signals for the master port of the TLB block
A.6. Write data channel signals for the master port of the PTW block
A.7. Write response channel signals
A.8. Read address channel signals
A.9. Read data channel signals for the slave port of the TLB block
A.10. Read data channel signals for the master port of the TLB block
A.11. Read data channel signals for the master port of the PTW block
A.12. Write address channel signals
A.13. Write data channel signals for the slave port of the TLB block
A.14. Write data channel signals for the master port of the TLB block
A.15. Write data channel signals for the master port of the PTW block
A.16. Write response channel signals
A.17. Read address channel signals
A.18. Read data channel signals for the slave port of the TLB block
A.19. Read data channel signals for the master port of the TLB block
A.20. Read data channel signals for the master port of the PTW block
A.21. Write address channel signals
A.22. Write data channel signals for the slave port of the TLB block
A.23. Write data channel signals for the master port of the TLB block
A.24. Write data channel signals for the master port of the PTW block
A.25. Write response channel signals
A.26. Read address channel signals
A.27. Read data channel signals for the slave port of the TLB block
A.28. Read data channel signals for the master port of the TLB block
A.29. Read data channel signals for the master port of the PTW block
A.30. Snoop channel signals
A.31. APB4 signals
A.32. APB3 signals
A.33. LPI signals
A.34. Sideband signals
A.35. Interrupt signals
A.36. MBIST signals
A.37. Authentication interface signal
A.38. Tie-off signals
A.39. Performance event signals
B.1. Issue A

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM® in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A14 March 2013First release for r0p0.
Copyright © 2013 ARM. All rights reserved.ARM DDI 0521A
Non-ConfidentialID051113