ARM® Cortex®-A17 MPCore Processor Technical Reference Manual

Revision: r1p0


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the Cortex-A17 MPCore processor
1.2. Compliance
1.2.1. ARM architecture
1.2.2. Advanced Microcontroller Bus Architectures
1.2.3. Debug architecture
1.2.4. Generic Timer architecture
1.3. Features
1.4. Interfaces
1.5. Implementation options
1.6. Product documentation and design flow
1.6.1. Documentation
1.6.2. Design flow
1.7. Product revisions
1.7.1. r0p0 - r1p0
2. Functional Description
2.1. About the Cortex-A17 MPCore processor functions
2.1.1. Processor components
2.2. Interfaces
2.2.1. ACE master interface
2.2.2. Accelerator Coherency Port AXI slave interface
2.2.3. Peripheral port AXI master interface
2.2.4. Interrupt inputs
2.2.5. Generic timer interface
2.2.6. Performance Monitoring Unit (PMU) interface
2.2.7. Debug APB interface
2.2.8. Program Trace Macrocell interface
2.2.9. DFT interface
2.2.10. MBIST interface
2.3. Clocking and resets
2.3.1. Clocks
2.3.2. Clock enables
2.3.3. Resets
2.4. Power management
2.4.1. Dynamic power management
2.4.2. State retention control
2.4.3. Power domains
2.4.4. Power modes
3. Programmers Model
3.1. About the programmers model
3.2. ThumbEE instruction set
3.3. Jazelle Extension
3.3.1. Register summary
3.3.2. Register description
3.4. Advanced SIMD and VFP Extensions
3.5. Security Extensions architecture
3.5.1. System boot sequence
3.5.2. Security Extensions write access disable
3.6. Virtualization Extensions architecture
3.7. Large Physical Address Extension architecture
3.8. Multiprocessing Extensions
3.9. Operating states
3.10. Memory model
4. System Control
4.1. About system control
4.2. Register summary
4.2.1. c0 registers
4.2.2. c1 registers
4.2.3. c2 registers
4.2.4. c3 registers
4.2.5. c4 registers
4.2.6. c5 registers
4.2.7. c6 registers
4.2.8. c7 registers
4.2.9. c8 registers
4.2.10. c9 registers
4.2.11. c10 registers
4.2.12. c11 registers
4.2.13. c12 registers
4.2.14. c13 registers
4.2.15. c14 registers
4.2.16. c15 registers
4.2.17. 64-bit registers
4.2.18. Identification registers
4.2.19. Virtual memory control registers
4.2.20. PL1 Fault handling registers
4.2.21. Other system control registers
4.2.22. Cache maintenance operations
4.2.23. TLB maintenance operations
4.2.24. Address translation operations
4.2.25. Miscellaneous operations
4.2.26. Performance monitor registers
4.2.27. Security Extensions registers
4.2.28. Virtualization Extensions registers
4.2.29. Hyp mode TLB maintenance operations
4.2.30. Generic Timer registers
4.2.31. Implementation defined registers
4.3. Register descriptions
4.3.1. Main ID Register
4.3.2. Cache Type Register
4.3.3. TCM Type Register
4.3.4. TLB Type Register
4.3.5. Multiprocessor Affinity Register
4.3.6. Revision ID Register
4.3.7. Processor Feature Register 0
4.3.8. Processor Feature Register 1
4.3.9. Debug Feature Register 0
4.3.10. Auxiliary Feature Register 0
4.3.11. Memory Model Feature Register 0
4.3.12. Memory Model Feature Register 1
4.3.13. Memory Model Feature Register 2
4.3.14. Memory Model Feature Register 3
4.3.15. Instruction Set Attribute Register 0
4.3.16. Instruction Set Attribute Register 1
4.3.17. Instruction Set Attribute Register 2
4.3.18. Instruction Set Attribute Register 3
4.3.19. Instruction Set Attribute Register 4
4.3.20. Instruction Set Attribute Register 5
4.3.21. Cache Size ID Register
4.3.22. Cache Level ID Register
4.3.23. Auxiliary ID Register
4.3.24. Cache Size Selection Register
4.3.25. Virtualization Processor ID Register
4.3.26. Virtualization Multiprocessor ID Register
4.3.27. System Control Register
4.3.28. Auxiliary Control Register
4.3.29. Coprocessor Access Control Register
4.3.30. Secure Configuration Register
4.3.31. Non-secure Access Control Register
4.3.32. Hyp System Control Register
4.3.33. Hyp Auxiliary Configuration Register
4.3.34. Hyp Debug Control Register
4.3.35. Hyp Coprocessor Trap Register
4.3.36. Hyp Auxiliary Configuration Register
4.3.37. Hyp Translation Control Register
4.3.38. Data Fault Status Register
4.3.39. Instruction Fault Status Register
4.3.40. Auxiliary Data Fault Status Register
4.3.41. Auxiliary Instruction Fault Status Register
4.3.42. Hyp Auxiliary Data Fault Status Syndrome Register
4.3.43. Hyp Auxiliary Instruction Fault Status Syndrome Register
4.3.44. Hyp Syndrome Register
4.3.45. Physical Address Register
4.3.46. Data Cache Clean and Invalidate All
4.3.47. L2 Control Register
4.3.48. L2 Extended Control Register
4.3.49. SCU Control Register
4.3.50. Peripheral port start address register
4.3.51. Peripheral port end address register
4.3.52. L2 Memory Error Syndrome Register
4.3.53. Auxiliary Memory Attribute Indirection Register 0
4.3.54. Auxiliary Memory Attribute Indirection Register 1
4.3.55. Hyp Auxiliary Memory Attribute Indirection Register 0
4.3.56. Hyp Auxiliary Memory Attribute Indirection Register 1
4.3.57. FCSE Process ID Register
5. Memory Management Unit
5.1. About the MMU
5.2. TLB organization
5.2.1. Instruction micro TLB
5.2.2. Data micro TLB
5.2.3. Unified main TLB
5.3. TLB match process
5.4. Memory access sequence
5.5. MMU enabling and disabling
5.6. Intermediate table walk cache
5.7. Memory types
5.8. Memory region attributes
6. L1 Memory System
6.1. About the L1 memory system
6.2. Cache features
6.3. L1 instruction memory system
6.3.1. Instruction cache disabled behavior
6.3.2. Instruction cache speculative memory accesses
6.3.3. Program flow prediction
6.3.4. Enabling program flow prediction
6.4. L1 data memory system
6.4.1. Behavior for different memory types
6.4.2. Internal exclusive monitor
6.5. Data prefetching
6.5.1. PLD, PLDW, and PLI instructions
6.5.2. Data prefetching and monitoring
6.6. Direct access to internal memory
6.6.1. Data cache tag and data encoding
6.6.2. Instruction cache tag and data encoding
6.6.3. TLB data encoding
7. L2 Memory System
7.1. About the L2 Memory system
7.2. L2 cache
7.2.1. L2 error correction
7.2.2. L2 hardware cache flush
7.2.3. L2 cache RAM latency settings
7.3. Cache coherency
7.4. ACE master interface
7.4.1. Memory interface attributes
7.4.2. ACE transfers
7.4.3. AXI transaction IDs
7.4.4. Write response
7.4.5. AXI privilege information
7.4.6. AXI3 Compatibility mode
7.4.7. ACE configuration signals
7.5. ACP
7.5.1. Accelerator Coherency Port Interface Restrictions
7.5.2. ACP requests
7.5.3. ACP read and write acceptance
7.6. Peripheral port
7.6.1. Mapping the peripheral port
7.6.2. Peripheral port read issuing capability
7.6.3. Inter-dependencies between the Peripheral Port and the ACE master interface
7.7. External aborts and asynchronous errors
7.7.1. External aborts
7.7.2. Asynchronous errors
8. Generic Timer
8.1. About the Generic Timer
8.2. Generic Timer functional description
8.3. Timer programmers model
9. Debug
9.1. About debug
9.1.1. Debug host
9.1.2. Protocol converter
9.1.3. Debug target
9.1.4. The debug unit
9.2. Debug register interfaces
9.2.1. Processor interfaces
9.2.2. Breakpoints and watchpoints
9.2.3. Effects of resets on debug registers
9.3. Debug register summary
9.4. Debug register descriptions
9.4.1. Debug Identification Register
9.4.2. Program Counter Sampling Register
9.4.3. Debug Run Control Register
9.4.4. Breakpoint Value Registers
9.4.5. Breakpoint Control Registers
9.4.6. Watchpoint Value Registers
9.4.7. Watchpoint Control Registers
9.4.8. Debug ROM Address Register
9.4.9. Breakpoint Extended Value Registers
9.4.10. OS Lock Access Register
9.4.11. OS Lock Status Register
9.4.12. Device Powerdown and Reset Control Register
9.4.13. Debug Self Address Offset Register
9.4.14. Claim Tag Set Register
9.4.15. Claim Tag Clear Register
9.4.16. Debug Device ID Register 1
9.4.17. Debug Device ID Register 0
9.4.18. Debug Peripheral Identification Registers
9.4.19. Debug Component Identification Registers
9.5. Debug events
9.5.1. Watchpoint debug events
9.5.2. Asynchronous aborts
9.5.3. Debug OS lock
9.6. External debug interface
9.6.1. Memory map
9.6.2. Changing the authentication signals
10. Performance Monitoring Unit
10.1. About the Performance Monitoring Unit
10.2. PMU functional description
10.2.1. Event interface
10.2.2. CP15 and APB interface
10.2.3. Counters
10.3. PMU registers summary
10.4. PMU register descriptions
10.4.1. Performance Monitor Control Register
10.4.2. Performance Monitors Peripheral Identification Registers
10.4.3. Performance Monitors Component Identification Registers
10.5. Events
10.6. Interrupts
10.7. Exporting PMU events
10.7.1. External hardware
10.7.2. Debug trace hardware
11. Program Trace Macrocell
11.1. About PTM
11.2. PTM options
11.3. PTM functional description
11.3.1. Processor interface
11.3.2. Trace generation
11.3.3. Filtering and triggering resources
11.3.4. FIFO
11.3.5. Trace out
11.4. Reset
11.5. PTM programmers model
11.5.1. Programming the PTM
11.5.2. Event definitions
11.5.3. Turning off the PTM
11.5.4. Interaction with the performance monitoring unit
11.5.5. Effect of debug OS double lock on trace register access
11.6. Register summary
11.7. Register descriptions
11.7.1. Main Control Register
11.7.2. Configuration Code Register
11.7.3. System Configuration Register
11.7.4. TraceEnable Start/Stop Control Register
11.7.5. TraceEnable Control Register 1
11.7.6. Synchronization Frequency Register
11.7.7. ETM ID Register
11.7.8. Configuration Code Extension Register
11.7.9. Extended External Input Selection Register
11.7.10. Auxiliary Control Register
11.7.11. Power Down Control Register
11.7.12. Miscellaneous Output Register
11.7.13. Miscellaneous Input Register
11.7.14. Trigger Register
11.7.15. ATB Data Register 0
11.7.16. ATB Control Register 2
11.7.17. ATB Identification Register
11.7.18. ATB Control Register 0
11.7.19. Integration Mode Control Register
11.7.20. Peripheral Identification Registers
11.7.21. Component Identification Registers
12. Cross Trigger
12.1. About the cross trigger
12.2. Trigger inputs and outputs
12.3. Cortex-A17 CTI
12.4. Cortex-A17 CTM
13. NEON and Floating-point Unit
13.1. About NEON and floating-point unit
13.1.1. Advanced SIMDv2 support
13.1.2. VFPv4 support
13.2. Programmers model for NEON and floating-point unit
13.2.1. Accessing the Advanced SIMD and VFP feature identification registers
13.2.2. Enabling Advanced SIMD and VFP extensions
13.2.3. Register summary
13.2.4. Register descriptions
A. Signal Descriptions
A.1. About the signal descriptions
A.2. Clock and reset signals
A.3. Configuration signals
A.4. Interrupt signals
A.5. Asynchronous error signals
A.6. Generic Timer signals
A.7. Power control signals
A.8. ACE master interface signals
A.8.1. Clock and configuration signals
A.8.2. Write address channel signals
A.8.3. Write data channel signals
A.8.4. Write data response channel signals
A.8.5. Read address channel signals
A.8.6. Read data channel signals
A.8.7. Snoop address channel signals
A.8.8. Snoop response channel signals
A.8.9. Snoop data channel signals
A.8.10. Read/write acknowledge signals
A.9. Peripheral port AXI master interface signals
A.9.1. Clock and configuration signals
A.9.2. Write address channel signals
A.9.3. Write data channel signals
A.9.4. Write data response channel signals
A.9.5. Read address channel signals
A.9.6. Read data channel signals
A.10. ACP slave interface signals
A.10.1. Clock and configuration signals
A.10.2. Write address channel signals
A.10.3. Write data channel signals
A.10.4. Write response channel signals
A.10.5. Read address channel signals
A.10.6. Read data channel signals
A.11. External debug interface
A.11.1. APB Interface signals
A.11.2. Debug authentication interface signals
A.11.3. Miscellaneous Debug signals
A.11.4. PTM interface signals
A.11.5. PMU signals
A.12. Cross trigger channel interface
A.13. DFT interface signals
A.14. MBIST interface signals
B. Revisions

List of Figures

1. Key to timing diagram conventions
1.1. Multiprocessor block diagram
2.1. Cortex-A17 MPCore processor top-level diagram
2.2. CLK and CORECLK 1:2 relationship
2.3. CLK to CORECLK 1:4 relationship
2.4. CLK and L2RAMCLKEN relationship
2.5. CLK to L2RAMCLK 1:4 relationship
2.6. CORECLK and PCLKENDBG relationship
2.7. CORECLK and PCLKDBG 1:4 relationship
2.8. ACLKENM with CLK:ACLKM ratio changing from 3:1 to 1:1
2.9. Powerup reset timing
2.10. STANDBYWFI deassertion timing
2.11. L2 Wait For Interrupt timing
2.12. Successful retention timing
2.13. Denied retention timing
2.14. L2 dynamic retention timing
2.15. Power domains
4.1. MIDR bit assignments
4.2. CTR bit assignments
4.3. TLBTR bit assignments
4.4. MPIDR bit assignments
4.5. REVIDR bit assignments
4.6. ID_PFR0 bit assignments
4.7. ID_PFR1 bit assignments
4.8. ID_DFR0 bit assignments
4.9. ID_MMFR0 bit assignments
4.10. ID_MMFR1 bit assignments
4.11. ID_MMFR2 bit assignments
4.12. ID_MMFR3 bit assignments
4.13. ID_ISAR0 bit assignments
4.14. ID_ISAR1 bit assignments
4.15. ID_ISAR2 bit assignments
4.16. ID_ISAR3 bit assignments
4.17. ID_ISAR4 bit assignments
4.18. CCSIDR bit assignments
4.19. CLIDR bit assignments
4.20. CSSELR bit assignments
4.21. VPIDR bit assignments
4.22. VMPIDR bit assignments
4.23. SCTLR bit assignments
4.24. ACTLR bit assignments
4.25. CPACR bit assignments
4.26. SCR bit assignments
4.27. NSACR bit assignments
4.28. HSCTLR bit assignments
4.29. HDCR bit assignments
4.30. HCPTR bit assignments
4.31. DFSR bit assignments for Short-descriptor translation table format
4.32. DFSR bit assignments for Long-descriptor translation table format
4.33. IFSR bit assignments for Short-descriptor translation table format
4.34. IFSR bit assignments for Long-descriptor translation table format
4.35. HSR bit assignments
4.36. DCCIALL bit assignments
4.37. L2CTLR bit assignments
4.38. L2ECTLR bit assignments
4.39. SCUCTLR bit assignments
4.40. FILASTARTR bit assignments
4.41. FILAENDR bit assignments
4.42. L2MRERRSR bit assignment
7.1. L2 hardware cache flush timing
9.1. Typical debug system
9.2. DBGDIDR bit assignments
9.3. DBGPCSR bit assignments
9.4. DBGDRCR bit assignments
9.5. DBGBVR bit assignments
9.6. DBGBCR bit assignments
9.7. DBGWVR bit assignments
9.8. DBGWCR bit assignments
9.9. DBGDRAR 32-bit assignments
9.10. DBGDRAR 64-bit assignments
9.11. DBGBXVR bit assignments
9.12. DBGOSLAR bit assignments
9.13. DBGOSLSR bit assignments
9.14. DBGPRCR bit assignments
9.15. DBGDSAR 32-bit assignments
9.16. DBGDSAR 64-bit assignments
9.17. DBGCLAIMSET bit assignments
9.18. DBGCLAIMCLR bit assignments
9.19. DBGDEVID1 bit assignments
9.20. DBGDEVID0 bit assignments
9.21. External debug interface, including APBv3 slave port
10.1. PMU block diagram
10.2. Performance Monitor Control Register bit assignments
11.1. PTM functional blocks
11.2. ETMCR bit assignments
11.3. ETMCCR bit assignments
11.4. ETMSCR bit assignments
11.5. ETMSSCR bit assignments
11.6. ETMECR1 bit assignments
11.7. ETMIDR bit assignments
11.8. ETMCCER bit assignments
11.9. ETMEXTINSELR bit assignments
11.10. ETMAUXCR bit assignments
11.11. ETMPDCR bit assignments
11.12. ITMISCOUT bit assignments
11.13. ITMISCIN bit assignments
11.14. ITTRIGGER bit assignments
11.15. ITATBDATA0 bit assignments
11.16. ITATBCTR2 bit assignments
11.17. ITATBID bit assignments
11.18. ITATBCTR0 bit assignments
12.1. Debug system components
13.1. FPSID bit assignments
13.2. FPSCR bit assignments
13.3. MVFR1 bit assignments
13.4. MVFR0 bit assignments
13.5. FPEXC bit assignments

List of Tables

1. Typographical conventions
1.1. Implementation options for the Cortex-A17 MPCore processor RTL
2.1. Individual processor resets
2.2. Multiprocessor resets
2.3. Valid reset combinations
2.4. Clocks and reset domains
2.5. Supported power modes
3.1. Summary of Jazelle Extension registers
3.2. JIDR Register bit assignments
3.3. JOSCR Register bit assignments
3.4. JMCR Register bit assignments
3.5. CPSR J and T bit encoding
4.1. System control register field values
4.2. c0 register summary
4.3. c1 register summary
4.4. c2 register summary
4.5. c3 register summary
4.6. c5 register summary
4.7. c6 register summary
4.8. c7 register summary
4.9. c8 register summary
4.10. c9 register summary
4.11. c10 register summary
4.12. c10 register summary
4.13. c13 register summary
4.14. c15 register summary
4.15. 64-bit register summary
4.16. Identification registers
4.17. Virtual memory control registers
4.18. PL1 Fault handling registers
4.19. Other system control registers
4.20. Cache and branch predictor maintenance operations
4.21. TLB maintenance operations
4.22. Address translation operations
4.23. Miscellaneous system control operations
4.24. Performance monitor registers
4.25. Security Extensions registers
4.26. Virtualization Extensions registers
4.27. Hyp mode TLB maintenance operations
4.28. Memory access registers
4.29. MIDR bit assignments
4.30. CTR bit assignments
4.31. TLBTR bit assignments
4.32. MPIDR bit assignments
4.33. REVIDR bit assignments
4.34. ID_PFR0 bit assignments
4.35. ID_PFR1 bit assignments
4.36. ID_DFR0 bit assignments
4.37. ID_MMFR0 bit assignments
4.38. ID_MMFR1 bit assignments
4.39. ID_MMFR2 bit assignments
4.40. ID_MMFR3 bit assignments
4.41. ID_ISAR0 bit assignments
4.42. ID_ISAR1 bit assignments
4.43. ID_ISAR2 bit assignments
4.44. ID_ISAR3 bit assignments
4.45. ID_ISAR4 bit assignments
4.46. CCSIDR bit assignments
4.47. CCSIDR encodings
4.48. CLIDR bit assignments
4.49. CSSELR bit assignments
4.50. VPIDR bit assignments
4.51. VMPIDR bit assignments
4.52. SCTLR bit assignments
4.53. ACTLR bit assignments
4.54. CPACR bit assignments
4.55. SCR bit assignments
4.56. NSACR bit assignments
4.57. HSCTLR bit assignments
4.58. HDCR bit assignments
4.59. HCPTR bit assignments
4.60. DFSR bit assignments for Short-descriptor translation table format
4.61. DFSR bit assignments for Long-descriptor translation table format
4.62. Encodings of LL bits associated with the MMU fault
4.63. IFSR bit assignments for Long-descriptor translation table format
4.64. IFSR bit assignments for Long-descriptor translation table format
4.65. Encodings of LL bits associated with the MMU fault
4.66. HSR bit assignments
4.67. DCCIALL bit assignments
4.68. L2CTLR bit assignments
4.69. L2ECTLR bit assignments
4.70. SCUCTLR bit assignments
4.71. FILASTARTR bit assignments
4.72. FILAENDR bit assignments
4.73. L2MRERRSR bit assignment
5.1. TEX, C, and B encodings when SCTLR.TRE is set to 0
6.1. Memory attribute combinations
6.2. Cortex-A17 MPCore system coprocessor CP15 registers used to access internal memory
6.3. Data cache tag and data location encoding
6.4. Data cache tag data format
6.5. Instruction cache tag and data location encoding
6.6. Instruction cache tag data format
6.7. TLB Data Read Operation Register location encoding
6.8. TLB regular format encoding
6.9. TLB Walk format encoding
6.10. TLB IPA format encoding
6.11. Memory attributes
7.1. ACE master interface attributes
7.2. Encoding for AWIDM[7:0] and AWIDMP[7:0]
7.3. Encoding for ARIDM[7:0] and ARIDMP[7:0]
7.4. Processor mode and ARPROT and AWPROT values
7.5. Supported ACE configurations
7.6. Supported features in the ACE configurations
8.1. Generic Timer registers
9.1. CP14 debug register summary
9.2. DBGDIDR bit assignments
9.3. DBGPCSR bit assignments
9.4. DBGDRCR bit assignments
9.5. DBGBVR bit assignments when register is used for address comparison
9.6. DBGBVR bit assignments when register is used for Context matching
9.7. DBGBCR bit assignments
9.8. DBGWVR bit assignments
9.9. DBGWCR bit assignments
9.10. DBGDRAR bit assignments
9.11. DBGBXVR bit assignments
9.12. DBGOSLAR bit assignments
9.13. DBGOSLSR bit assignments
9.14. DBGPRCR bit assignments
9.15. DBGDSAR bit assignments
9.16. DBGCLAIMSET bit assignments
9.17. DBGCLAIMCLR bit assignments
9.18. DBGDEVID1 bit assignments
9.19. DBGDEVID0 bit assignments
9.20. Summary of the Debug Peripheral Identification Registers
9.21. Summary of the Component Identification Registers
9.22. Address mapping for debug trace components
10.1. PMU register summary
10.2. PMCR bit assignments
10.3. Summary of the Performance Monitors Peripheral Identification Registers
10.4. Summary of the Performance Monitors Component ID Registers
10.5. Performance monitor events
11.1. Cortex-A17 MPCore processor PTM implementation options
11.2. Event resource definitions
11.3. PTM register summary
11.4. ETMCR bit assignments
11.5. ETMCCR bit assignments
11.6. ETMSCR bit assignments
11.7. ETMSSCR bit assignments
11.8. ETMECR1 bit assignments
11.9. ID Register bit assignments
11.10. ETMCCER bit assignments
11.11. ETMEXTINSELR bit assignments
11.12. ETMAUXCR bit assignments
11.13. ETMPDCR bit assignments
11.14. ITMISCOUT bit assignments
11.15. ITMISCIN bit assignments
11.16. ITTRIGGER bit assignments
11.17. ITATBDATA0 bit assignments
11.18. ITATBCTR2 bit assignments
11.19. ITATBID bit assignments
11.20. ITATBCTR0 bit assignments
11.21. Summary of the Peripheral ID Registers
11.22. Summary of the Component Identification Registers
12.1. Trigger inputs
12.2. Trigger outputs
13.1. Advanced SIMD and VFP feature identification registers
13.2. Advanced SIMD and VFP system registers
13.3. FPSID bit assignments
13.4. FPSCR bit assignments
13.5. MVFR1 bit assignments 
13.6. MVFR0 bit assignments 
13.7. FPEXC bit assignments 
A.1. Clock and reset signals
A.2. Configuration signals
A.3. Interrupt signals
A.4. Asynchronous error signals
A.5. Generic Timer signals
A.6. Power control signals
A.7. Clock and configuration signals
A.8. address channel signals
A.9. Write data channel signals
A.10. Write data response channel signals
A.11. Read address channel signals
A.12. Read data channel signals
A.13. Snoop address channel signals
A.14. Snoop response channel signals
A.15. Snoop data channel signals
A.16. Read/write acknowledge signals
A.17. Clock and configuration signals
A.18. address channel signals
A.19. Write data channel signals
A.20. Write data response channel signals
A.21. Read address channel signals
A.22. Read data channel signals
A.23. Clock and configuration signals
A.24. Write address channel signals
A.25. Write data channel signals
A.26. Write response channel signals
A.27. Read address channel signals
A.28. Read data channel signals
A.29. APB Interface signals
A.30. Debug authentication interface signals
A.31. Miscellaneous Debug signals
A.32. ATB interface signals
A.33. Miscellaneous PTM interface signals
A.34. Performance Monitoring Unit signals
A.35. Cross trigger channel interface signals
A.36. DFT interface signals
A.37. MBIST interface signals
A.38. MBIST L1 interface signals
A.39. MBIST L2 Data and Buffer interface signals
A.40. MBIST L2 Tag and SCU interface signals
B.1. Issue A
B.2. Differences between issue A and issue B

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Revision History
Revision A11 March 2014First release for r0p0
Revision B28 June 2014First release for r1p0
Copyright © 2014 ARM. All rights reserved.ARM DDI 0535B
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