7.2. Debug register summary

Table 7.7 shows the debug registers. Each of these registers is 32 bits wide.

Table 7.7. Debug registers summary

NameDescription
DAUTHCTRL

Debug Authentication Control Register in the ARM®v8-M Architecture Reference Manual.

Note

This register is accessible by software from the Cortex-M23 processor and is RAZ/WI when accessed from the debugger.

DAUTHSTATUSDebug Authentication Status Register in the ARM®v8-M Architecture Reference Manual.
DDEVARCHDevice Architecture Register in the ARM®v8-M Architecture Reference Manual.
DFSRDebug Fault Status Register in the ARM®v8-M Architecture Reference Manual.
DHCSRDebug Halting Control and Status Register in the ARM®v8-M Architecture Reference Manual.
DCRSRDebug Core Register Select Register in the ARM®v8-M Architecture Reference Manual.
DCRDRDebug Core Register Data Register in the ARM®v8-M Architecture Reference Manual.
DEMCRDebug Exception and Monitor Control Register in the ARM®v8-M Architecture Reference Manual.
DSCSRDebug Security Control and Status Register in the ARM®v8-M Architecture Reference Manual.

Table 7.8 shows the FPB registers. Each of these registers is 32 bits wide.

Table 7.8. FPB register summary

NameDescription
FP_CTRLFlash Patch Control Register in the ARM®v8-M Architecture Reference Manual.
FP_DEVARCHFPB Device Architecture Register in the ARM®v8-M Architecture Reference Manual.
FP_COMP0Flash Patch Comparator Registers in the ARM®v8-M Architecture Reference Manual.
FP_COMP1
FP_COMP2
FP_COMP3

Table 7.9 shows the DWT registers. Each of these registers is 32 bits wide.

Table 7.9. DWT register summary

NameDescription
DWT_CTRLDWT Control Register in the ARM®v8-M Architecture Reference Manual.
DWT_DEVARCHDWT Device Architecture Register in the ARM®v8-M Architecture Reference Manual.
DWT_CYCCNTDWT Cycle Count Register in the ARM®v8-M Architecture Reference Manual.
DWT_CPICNTDWT CPI Count Register in the ARM®v8-M Architecture Reference Manual.
DWT_EXCCNTDWT Exception Overhead Count Register in the ARM®v8-M Architecture Reference Manual.
DWT_SLEEPCNTDWT Sleep Count Register in the ARM®v8-M Architecture Reference Manual.
DWT_LSUCNTDWT LSU Count Register in the ARM®v8-M Architecture Reference Manual.
DWT_FOLDCNTDWT Folded Instruction Count Register in the ARM®v8-M Architecture Reference Manual.
DWT_PCSRDWT Program Counter Sample Register in the ARM®v8-M Architecture Reference Manual.
DWT_COMPnDWT Comparator Register in the ARM®v8-M Architecture Reference Manual.
DWT_FUNCTIONnDWT Function Register in the ARM®v8-M Architecture Reference Manual.

See the ARM® CoreSight™ ETM-M23 Technical Reference Manual for information about the ETM registers.

See the ARM® CoreSight™ MTB-M23 Technical Reference Manual for information about the MTB registers.

Table 7.10 shows the CTI registers. Each of these registers is 32 bits wide.

Table 7.10. CTI register summary

NameDescription
CTICONTROLSee the ARM® CoreSight™ SoC-400 Technical Reference Manual.
CTIINTACK
CTIAPPSET
CTIAPPCLEAR
CTIAPPPULSE
CTIINEN[7:0]
CTIINEN1
CTIOUTEN2[7:0]
CTITRIGINSTATUS
CTITRIGOUTSTATUS
CTICHINSTATUS
CTICHOUTSTATUS
CTIGATE
ASICCTL
ITCHINACK
ITTRIGINACK
ITCHOUT
ITTRIGOUT
ITCHOUTACK
ITTRIGOUTACK
ITCHIN
ITTRIGIN
ITCTRL
CLAIMSET
CLAIMCLR
LAR
LSR
AUTHSTATUS
DEVID
DEVARCH

See the ARM®v8-M Architecture Reference Manual for more information about the debug registers and their addresses, access types, and reset values.

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