7.1.4. Flash Patch and Breakpoint unit
The Cortex-M23 processor FPB implementation provides between
zero and four breakpoint registers. A processor that is configured
with zero breakpoints implements no breakpoint functionality and
the ROM table shows that no FPB is implemented.
The processor breakpoints implement PC-based breakpoint functionality,
as described in the ARM®v8-M
Architecture Reference Manual.
FPB CoreSight identification
Table 7.5 shows
the FPB identification registers and their values for debugger detection.
Table 7.5. FPB identification registers
| Address | Register | Value | Description |
|---|
0xE0002FD0 | Peripheral ID4 | 0x00000004 | See the ARM®v8-M Architecture Reference
Manual. |
0xE0002FE0 | Peripheral ID0 | 0x00000020 |
0xE0002FE4 | Peripheral ID1 | 0x000000BD |
0xE0002FE8 | Peripheral ID2 | 0x0000000B |
0xE0002FEC | Peripheral ID3 | 0x00000000 |
0xE0002FF0 | Component ID0 | 0x0000000D |
0xE0002FF4 | Component ID1 | 0x00000090 |
0xE0002FF8 | Component ID2 | 0x00000005 |
0xE0002FFC | Component ID3 | 0x000000B1 |
See the ARM®v8-M
Architecture Reference Manual and the CoreSight
SoC-400 Technical Reference Manual for more information
about the FPB CoreSight identification registers, and their addresses
and access types.
PDF version