7.1.4. Flash Patch and Breakpoint unit

The Cortex-M23 processor FPB implementation provides between zero and four breakpoint registers. A processor that is configured with zero breakpoints implements no breakpoint functionality and the ROM table shows that no FPB is implemented.

FPB functionality

The processor breakpoints implement PC-based breakpoint functionality, as described in the ARM®v8-M Architecture Reference Manual.

FPB CoreSight identification

Table 7.5 shows the FPB identification registers and their values for debugger detection.

Table 7.5. FPB identification registers

AddressRegisterValueDescription
0xE0002FD0Peripheral ID40x00000004See the ARM®v8-M Architecture Reference Manual.
0xE0002FE0Peripheral ID00x00000020
0xE0002FE4Peripheral ID10x000000BD
0xE0002FE8Peripheral ID20x0000000B
0xE0002FECPeripheral ID30x00000000
0xE0002FF0Component ID00x0000000D
0xE0002FF4Component ID10x00000090
0xE0002FF8Component ID20x00000005
0xE0002FFCComponent ID30x000000B1

See the ARM®v8-M Architecture Reference Manual and the CoreSight SoC-400 Technical Reference Manual for more information about the FPB CoreSight identification registers, and their addresses and access types.

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