7.1.2. System Control Space

If debug is implemented, the processor provides debug through registers in the SCS, see Debug register summary.

SCS CoreSight identification

Table 7.3 shows the SCS CoreSight identification registers and values for debugger detection. Final debugger identification of the Cortex-M23 processor is through the CPUID register in the SCS, see CPUID Register.

Table 7.3. SCS identification values

0xE000EFD0Peripheral ID40x00000004See the ARM®v8-M Architecture Reference Manual.
0xE000EFE0Peripheral ID00x00000020
0xE000EFE4Peripheral ID10x000000BD
0xE000EFE8Peripheral ID20x0000000B
0xE000EFECPeripheral ID30x00000000
0xE000EFF0Component ID00x0000000D
0xE000EFF4Component ID10x00000090
0xE000EFF8Component ID20x00000005
0xE000EFFCComponent ID30x000000B1

See the ARM®v8-M Architecture Reference Manual and the CoreSight SoC-400 Technical Reference Manual for more information about the SCS CoreSight identification registers, and their addresses and access types.

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